ISP1583 Просмотр технического описания (PDF) - NXP Semiconductors.

Номер в каталоге

Компоненты Описание

Список матч

ISP1583

Hi-Speed USB peripheral controller

NXP Semiconductors. 

NXP Semiconductors

ISP1583

Hi-Speed USB peripheral controller

8. Functional description

The ISP1583 is a high-speed USB peripheral controller. It implements the Hi-Speed USB

or the Original USB physical layer, and the packet protocol layer. It concurrently maintains

up to 16 USB endpoints (control IN, control OUT, and seven IN and seven OUT

configurable) along with endpoint EP0 set up, which accesses the set-up buffer. The Ref.

1 “Universal Serial Bus Specification Rev. 2.0”, Chapter 9 protocol handling is executed

using the external firmware.

The ISP1583 has a fast general-purpose interface to communicate with most types of

microcontrollers and microprocessors. This microcontroller interface is configured using

pins BUS_CONF/DA0, MODE1 and MODE0/DA1 to accommodate most interface types.

Two bus configurations are available, selected using input BUS_CONF/DA0 during

power-up:

• Generic processor mode (pin BUS_CONF/DA0 = HIGH):

– AD[7:0]: 8-bit address bus (selects target register)

– DATA[15:0]: 16-bit data bus (shared by processor and DMA)

– Control signals: RW_N and DS_N or RD_N and WR_N (selected using pin

MODE0/DA1), CS_N

– DMA interface (generic slave mode only): Uses lines DATA[15:0] as data bus,

DIOR and DIOW as dedicated read and write strobes

• Split bus mode (pin BUS_CONF/DA0 = LOW):

– AD[7:0]: 8-bit local microprocessor bus (multiplexed address and data)

– DATA[15:0]: 16-bit DMA data bus

– Control signals: CS_N, ALE or A0 (selected using pin MODE1), RW_N and DS_N

or RD_N and WR_N (selected using pin MODE0/DA1)

– DMA interface (master or slave mode): Uses DIOR and DIOW as dedicated read

and write strobes

For high-bandwidth data transfer, the integrated DMA handler can be invoked to transfer

data to or from external memory or devices. The DMA interface can be configured by

writing to proper DMA registers (see Section 9.4).

The ISP1583 supports Hi-Speed USB and Original USB signaling. The USB signaling

speed is automatically detected.

The ISP1583 has 8 kB of internal FIFO memory, which is shared among enabled USB

endpoints, including control IN and control OUT endpoints, and set-up token buffer.

There are seven IN and seven OUT configurable endpoints, and two fixed control

endpoints that are 64 bytes long. Any of the seven IN and seven OUT endpoints can be

separately enabled or disabled. The endpoint type (interrupt, isochronous or bulk) and

packet size of these endpoints can be individually configured, depending on the

requirements of the application. Optional double buffering increases the data throughput

of these data endpoints.

The ISP1583 requires 3.3 V power supply. It has 5 V tolerant I/O pads and an internal

1.8 V regulator to power the digital logic. The I/O voltage can range from 1.65 V to 3.6 V.

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

© NXP B.V. 2008. All rights reserved.

12 of 99

Share Link: