IDT71V416YL Просмотр технического описания (PDF) - Integrated Device Technology

Номер в каталоге

Компоненты Описание

Список матч

IDT71V416YL

3.3V CMOS Static RAM 4 Meg (256K x 16-Bit)

Integrated Device Technology 

IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM

4 Meg (256K x 16-Bit)

Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,3)

tWC

ADDRESS

CS

BHE, BLE

tAW

tAS

tCW (2)

tBW

tWP

tWR

WE

DATAOUT

DATAIN

tDH

tDW

DATAIN VALID

6442 drw 0

Timing Waveform of Write Cycle No. 3

(BHE, BLE Controlled Timing)(1,3)

ADDRESS

CS

BHE, BLE

tWC

tAW

tCW (2)

tAS

tBW

tWP

tWR

WE

DATAOUT

tDW

tDH

DATAIN

DATAIN VALID

6442 drw 1

NOTES:

1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.

2. During this period, I/O pins are in the output state, and input signals must not be applied.

3. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

6.742

Share Link: