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IDT71V416YL Просмотр технического описания (PDF) - Integrated Device Technology

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IDT71V416YL
IDT
Integrated Device Technology IDT
IDT71V416YL Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
71V416S/L10(2)
71V416S/L12
71V416S/L15
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
10
____
12
____
15
____
ns
tAA
Address Access Time
____
10
____
12
____
15
ns
tACS
tCLZ(1)
tCHZ(1)
Chip Select Access Time
Chip Select Low to Output in Low-Z
Chip Select High to Output in High-Z
____
10
____
12
____
15
ns
4
____
4
____
4
____
ns
____
5
____
6
____
7
ns
tOE
tOLZ(1)
tOHZ(1)
Output Enable Low to Output Valid
Output Enable Low to Output in Low-Z
Output Enable High to Output in High-Z
____
5
____
6
____
7
ns
0
____
0
____
0
____
ns
____
5
____
6
____
7
ns
tOH
Output Hold from Address Change
4
____
4
____
4
____
ns
tBE
tBLZ(1)
tBHZ(1)
Byte Enable Low to Output Valid
Byte Enable Low to Output in Low-Z
Byte Enable High to Output in High-Z
____
5
____
6
____
7
ns
0
____
0
____
0
____
ns
____
5
____
6
____
7
ns
WRITE CYCLE
tWC
Write Cycle Time
10
____
12
____
15
____
ns
tAW
Address Valid to End of Write
8
____
8
____
10
____
ns
tCW
Chip Select Low to End of Write
8
____
8
____
10
____
ns
tBW
Byte Enable Low to End of Write
8
____
8
____
10
____
ns
tAS
Address Set-up Time
0
____
0
____
0
____
ns
tWR
Address Hold from End of Write
0
____
0
____
0
____
ns
tWP
Write Pulse Width
8
____
8
____
10
____
ns
tDW
Data Valid to End of Write
5
____
6
____
7
____
ns
tDH
tOW(1)
tWHZ(1)
Data Hold Time
Write Enable High to Output in Low-Z
Write Enable Low to Output in High-Z
0
____
0
____
0
____
ns
3
____
3
____
3
____
ns
____
6
____
7
____
7
ns
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
2. Low power 10ns (L10) speed 0ºC to +70ºC temperature range only.
6442 tbl 10
Timing Waveform of Read Cycle No. 1(1,2,3)
tRC
ADDRESS
tAA
tOH
DATAOUT
PREVIOUS DATAOUT VALID
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. OE, BHE, and BLE are LOW.
6442d06
6.542
tOH
DATAOUT VALID

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