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IDT71V416YL12YGI

3.3V CMOS Static RAM 4 Meg (256K x 16-Bit)

Integrated Device Technology 

IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM

4 Meg (256K x 16-Bit)

Timing Waveform of Read Cycle No. 2(1)

ADDRESS

OE

CS

BHE, BLE

DATAOUT

tRC

tAA

tOE

(3)

tOLZ

tCLZ (3) tACS (2)

tBE (2)

(3)

tBLZ

Commercial and Industrial Temperature Ranges

tOH

tOHZ (3)

tCHZ (3)

tBHZ (3)

DATAOUT VALID

6442 drw 07

NOTES:

1. WE is HIGH for Read Cycle.

2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter.

3. Transition is measured ±200mV from steady state.

Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)

ADDRESS

tWC

tAW

CS

BHE, BLE

WE

tCW (2)

tBW

tWP

(5)

tCHZ

tWR

(5)

tBHZ

DATAOUT

DATAIN

tAS

tWHZ (5)

PREVIOUS DATA VALID (3)

(5)

tOW

tDW

tDH

DATAIN VALID

DATA VALID

6442 drw 0

NOTES:

1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.

2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data

to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as

short as the specified tWP.

3. During this period, I/O pins are in the output state, and input signals must not be applied.

4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

5. Transition is measured ±200mV from steady state.

6.462

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