70P2352-IGT Просмотр технического описания (PDF) - Teridian Semiconductor Corporation
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70P2352-IGT Datasheet PDF : 42 Pages
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78P2352
Dual Channel
OC-3/ STM1-E/ E4 LIU
REGISTER DESCRIPTION (CONTINUED)
ADDRESS N-1: SIGNAL CONTROL REGISTER
BIT
NAME
TYPE
DFLT
VALUE
DESCRIPTION
7 TCMIINV R/W
Transmit CMI Inversion:
This bit will flip the polarity of the transmit CMI data outputs at CMIxP/N.
0 For debug use only.
0: Normal
1: Invert
6 RCMIINV R/W
Receive CMI Inversion:
This bit will flip the polarity of the receive CMI data inputs at RXxP/N. For
0 debug use only.
0: Normal
1: Invert
5 LOLOR R/W
Receive Loss of Lock/Signal Override:
When high, the RXLOL and RXLOS signals will always remain low.
0: Normal
0
1: Forces LOS and LOL outputs to be low and resets counters
NOTE: For reliable operation of the Rx LOL detection circuitry, one must
manually reset the LOL counter by toggling this bit upon power-up or
initialization.
Analog Loopback Selection:
4 RLBK R/W
0
RLBK LLBK
0
0 Normal operation
1
0 Remote Loopback Enable: Recovered receive data
3 LLBK R/W
0
is looped back to the transmit driver for retransmission.
0
1 Local Loopback Enable: The transmit data is
looped back and used as the input to the receiver.
2 RCLKP R/W
Receive Clock Inversion Select:
0
This bit will invert the receive output clock.
0: Normal. Data clocked out on falling edge of receive clock.
1: Invert. Data clocked out on the rising edge of receive clock.
1 TCLKP R/W
Transmit Clock Inversion Select:
0
This bit will invert the transmit input system clock.
0: Normal. Data is clocked in on rising edge of the transmit clock.
1: Invert. Data is clocked in on the falling edge of the transmit clock.
0 FRST R/W
FIFO Reset:
0: Normal operation
1: Reset FIFO pointers to default locations.
0
This reset should be initiated anytime the transmitter or IC powers up to
ensure the FIFO is centered after internal VCO clocks and external
transmit clocks are stable.
*Not required for Plesiochronous Serial Mode
Page: 13 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
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