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MT8960

Integrated PCM Filter Codec

Zarlink Semiconductor Inc 

MT8960/61/62/63/64/65/66/67

Data Sheet

AC Electrical Characteristics - Transmit (A/D) Path - Voltages are with respect to GNDD unless otherwise stated.

TA=0 to 70°C, VDD=5V±5%, VEE=-5V±5%, VRef=2.5V±0.5%, GNDA=GNDD=0V, Clock Frequency = 2.048MHz,

Filter Gain Setting = 0dB. Outputs unloaded unless otherwise specified.

A Quantization

CCITT G712

N Distortion

(Method 2)

A (cont’d)

AT&T

L (See Figure 13)

O

G

DQX2

35.30

29.30

24.30

Sinusoidal Input Level:

dB 0 to -30 dBm0

dB -40 dBm0

dB -45 dBm0

12

Intermodulation CCITT G712 IMDX

Distortion

50/60 Hz

1

-55

dB 50/60 Hz @ -23 dBm0

and any signal within

300-3400 Hz at -9

dBm0

CCITT G712

2 tone

IMDX

2

-41

dB 740 Hz and 1255 Hz

@ -4 to -21 dBm0.

Equal Input Levels

AT&T

IMDX

3

4 tone

IMDX

4

13

Gain Relative to ≤50 Hz

GRX

Gain @ 1004 Hz 60 Hz

(See Figure 10) 200 Hz

-1.8

300-3000 Hz

-

3200 Hz

0.125

3300 Hz

-

3400 Hz

0.275

4000 Hz

-

≥4600 Hz

0.350

-0.80

-47

dB 2nd order products

-49

dB 3rd order products

-25

dB 0 dBm0 Input Signal

-30

dB

0.00

dB Transmit

0.125 dB Filter

0.125 dB Response

0.030 dB

-

dB

0.100 dB

-14

dB

-32

14

Crosstalk D/A to A/D

CTRT

-70

dB 0 dBm0 @ 1.02 kHz

in D/A

15

Power Supply

Rejection

VDD PSS 33

VEE

R1

35

PSS

R2

dB

Input 50 mVRMS at

dB 1.02 kHz

16

Overload Distortion (See

Fig.15)

Input

frequency=1.02kHz

* Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing

Note 6:

0dBm0=1.185 VRMS for the µ-Law codec.

0dBm0=1.231 VRMS for the A-Law codec.

18

Zarlink Semiconductor Inc.

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