7030L Просмотр технического описания (PDF) - NXP Semiconductors.
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7030L Datasheet PDF : 12 Pages
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NXP Semiconductors
PH7030L
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2. Pinning information
Pin
Symbol Description
1
S
source
2
S
source
3
S
source
4
G
gate
mb
D
mounting base; connected to
drain
3. Ordering information
Simplified outline
mb
1234
SOT669
(LFPAK)
Graphic symbol
D
G
mbb076 S
Table 3. Ordering information
Type number
Package
Name
Description
PH7030L
LFPAK
plastic single-ended surface-mounted package (LFPAK); 4 leads
4. Limiting values
Version
SOT669
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
VDS
drain-source voltage
VGS
gate-source voltage
ID
drain current
IDM
peak drain current
Ptot
total power dissipation
Tstg
storage temperature
Tj
junction temperature
Source-drain diode
Tj ≥ 25 °C; Tj ≤ 150 °C
VGS = 10 V; Tmb = 25 °C; see Figure 1; see Figure 3
VGS = 10 V; Tmb = 100 °C; see Figure 1
tp ≤ 10 µs; pulsed; Tmb = 25 °C; see Figure 3
Tmb = 25 °C; see Figure 2
IS
source current
ISM
peak source current
Avalanche ruggedness
Tmb = 25 °C
tp ≤ 10 µs; pulsed; Tmb = 25 °C
EDS(AL)S
non-repetitive
VGS = 10 V; Tj(init) = 25 °C; ID = 33.9 A; Vsup ≤ 30 V;
drain-source avalanche unclamped; tp = 0.15 ms
energy
Min Max Unit
-
30
V
-20 20
V
-
68
A
-
43
A
-
220 A
-
62.5 W
-55 150 °C
-55 150 °C
-
52
A
-
150 A
-
115 mJ
PH7030L_5
Product data sheet
Rev. 05 — 29 June 2009
© NXP B.V. 2009. All rights reserved.
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