R5F61582 Просмотр технического описания (PDF) - Renesas Electronics
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R5F61582 Datasheet PDF : 796 Pages
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2.8.4 Index Register Indirect with Displacement—@(d:16,RnL.B), @(d:32,RnL.B),
@(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)..................... 54
2.8.5 Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment,
or Post-Decrement—@ERn+, @−ERn, @+ERn, or @ERn− ................................ 54
2.8.6 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32....................................... 55
2.8.7 Immediate—#xx ..................................................................................................... 56
2.8.8 Program-Counter Relative—@(d:8, PC) or @(d:16, PC) ...................................... 57
2.8.9 Program-Counter Relative with Index Register—@(RnL.B, PC), @(Rn.W, PC),
or @(ERn.L, PC) .................................................................................................... 57
2.8.10 Memory Indirect—@@aa:8 ............................................................................... 57
2.8.11 Extended Memory Indirect—@@vec:7 ............................................................. 58
2.8.12 Effective Address Calculation ............................................................................ 58
2.8.13 MOVA Instruction.............................................................................................. 60
2.9 Processing States.................................................................................................................. 61
Section 3 MCU Operating Modes ....................................................................... 63
3.1 Operating Mode Selection ................................................................................................... 63
3.2 Register Descriptions........................................................................................................... 63
3.2.1 Mode Control Register (MDCR) ............................................................................ 64
3.2.2 System Control Register (SYSCR)......................................................................... 65
3.3 Operating Mode Descriptions .............................................................................................. 67
3.3.1 Mode 1.................................................................................................................... 67
3.3.2 Mode 2.................................................................................................................... 67
3.3.3 Mode 3.................................................................................................................... 67
3.4 Address Map ........................................................................................................................ 68
3.4.1 Address Map........................................................................................................... 68
Section 4 Exception Handling ............................................................................. 69
4.1 Exception Handling Types and Priority............................................................................... 69
4.2 Exception Sources and Exception Handling Vector Table .................................................. 70
4.3 Reset .................................................................................................................................... 72
4.3.1 Reset Exception Handling ...................................................................................... 72
4.3.2 Interrupts after Reset............................................................................................... 73
4.3.3 On-Chip Peripheral Functions after Reset Release................................................. 73
4.4 Traces................................................................................................................................... 74
4.5 Address Error....................................................................................................................... 74
4.5.1 Address Error Source.............................................................................................. 74
4.5.2 Address Error Exception Handling......................................................................... 76
4.6 Interrupts.............................................................................................................................. 77
4.6.1 Interrupt Sources..................................................................................................... 77
4.6.2 Interrupt Exception Handling ................................................................................. 77
4.7 Instruction Exception Handling ........................................................................................... 78
4.7.1 Trap Instruction ...................................................................................................... 78
Rev. 2.00 Mar. 15, 2006 page x of xxxviii
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