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74ABT543A

Octal latched transceiver with dual enable; 3-state

NXP Semiconductors. 

NXP Semiconductors

74ABT543A

Octal latched transceiver with dual enable; 3-state

5. Pinning information

5.1 Pinning

Fig 4. Pin configuration

LEBA 1

OEBA 2

A0 3

A1 4

A2 5

A3 6

A4 7

A5 8

A6 9

A7 10

EAB 11

GND 12

74ABT543A

24 VCC

23 EBA

22 B0

21 B1

20 B2

19 B3

18 B4

17 B5

16 B6

15 B7

14 LEAB

13 OEAB

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5.2 Pin description

Table 2.

Symbol

LEBA

OEBA

A0 to A7

EAB

GND

OEAB

LEAB

B0 to B7

EBA

VCC

Pin description

Pin

1

2

3, 4, 5, 6, 7, 8, 9, 10

11

12

13

14

22, 21, 20, 19, 18, 17, 16, 15

23

24

Description

B-to-A latch enable input (active LOW)

B-to-A output enable input (active LOW)

data input or output

A-to-B enable input (active LOW)

ground (0 V)

A-to-B output enable input (active LOW)

A-to-B latch enable input (active LOW)

data input or output

B-to-A enable input (active LOW)

positive supply voltage

74ABT543A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 5 — 3 November 2011

© NXP B.V. 2011. All rights reserved.

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