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2N5060RLRMG Datasheet PDF : 7 Pages
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2N5060 Series
Sensitive Gate
Silicon Controlled Rectifiers
Reverse Blocking Thyristors
Annular PNPN devices designed for high volume consumer
applications such as relay and lamp drivers, small motor controls, gate
drivers for larger thyristors, and sensing and detection circuits.
Supplied in an inexpensive plastic TO−92/TO-226AA package which
is readily adaptable for use in automatic insertion equipment.
Features
• Sensitive Gate Trigger Current − 200 mA Maximum
• Low Reverse and Forward Blocking Current − 50 mA Maximum,
TC = 110°C
• Low Holding Current − 5 mA Maximum
• Passivated Surface for Reliability and Uniformity
• These are Pb−Free Devices
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Peak Repetitive Off−State Voltage (Note 1) VDRM,
V
(TJ = *40 to 110°C, Sine Wave,
VRRM
50 to 60 Hz, RGK = 1 kW)
2N5060
30
2N5061
60
2N5062
100
2N5064
200
On-State Current RMS (180° Conduction
IT(RMS)
0.8
A
Angles; TC = 80°C)
*Average On-State Current
(180° Conduction Angles)
IT(AV)
A
(TC = 67°C)
(TC = 102°C)
0.51
0.255
*Peak Non-repetitive Surge Current,
TA = 25°C (1/2 cycle, Sine Wave, 60 Hz)
ITSM
10
A
Circuit Fusing Considerations (t = 8.3 ms)
I2t
0.4
A2s
*Average On-State Current
IT(AV)
A
(180° Conduction Angles)
(TC = 67°C)
0.51
(TC = 102°C)
0.255
*Forward Peak Gate Power (Pulse Width v PGM
0.1
W
1.0 msec; TA = 25°C)
*Forward Average Gate Power
(TA = 25°C, t = 8.3 ms)
PG(AV)
0.01
W
*Forward Peak Gate Current (Pulse Width
IGM
1.0
A
v 1.0 msec; TA = 25°C)
*Reverse Peak Gate Voltage (Pulse Width
VRGM
5.0
V
v 1.0 msec; TA = 25°C)
*Operating Junction Temperature Range
TJ
−40 to
°C
+110
*Storage Temperature Range
Tstg
−40 to
°C
+150
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings
apply for zero or negative gate voltage; however, positive gate voltage shall
not be applied concurrent with negative potential on the anode. Blocking
voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.
*Indicates JEDEC Registered Data.
© Semiconductor Components Industries, LLC, 2011
1
September, 2011 − Rev. 10
http://onsemi.com
SILICON CONTROLLED
RECTIFIERS
0.8 A RMS, 30 − 200 V
G
A
K
MARKING
DIAGRAM
123
TO−92
CASE 29
STYLE 10
2N
50xx
YWW
50xx
Y
WW
Specific Device Code
= Year
= Work Week
PIN ASSIGNMENT
1
Cathode
2
Gate
3
Anode
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Publication Order Number:
2N5060/D
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