HEF4520BP,652 Просмотр технического описания (PDF) - NXP Semiconductors.

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HEF4520BP,652

Dual binary counter

NXP Semiconductors. 

NXP Semiconductors

HEF4520B

Dual binary counter

5. Pinning information

5.1 Pinning

Fig 4. Pin configuration

HEF4520B

1CP0 1

1CP1 2

1Q0 3

1Q1 4

1Q2 5

1Q3 6

1MR 7

VSS 8

16 VDD

15 2MR

14 2Q3

13 2Q2

12 2Q1

11 2Q0

10 2CP1

9 2CP0

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5.2 Pin description

Table 2. Pin description

Symbol

Pin

1CP0, 2CP0

1, 9

1CP1, 2CP1

2, 10

1Q0 to 1Q3

3, 4, 5, 6

1MR, 2MR

7, 15

VSS

2Q0 to 2Q3

8

11, 12, 13, 14

VDD

16

6. Functional description

Description

clock input (LOW-to-HIGH triggered)

clock input (HIGH-to-LOW triggered)

output

master reset input

ground supply voltage

output

supply voltage

Table 3.

nCP0



L



X



H

X

Function table[1]

nCP1

H



X



L



X

nMR

L

L

L

L

L

L

H

Mode

counter advances

counter advances

no change

no change

no change

no change

nQ0 to nQ3 = LOW

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care;  = positive-going transition;  = negative-going transition.

HEF4520B

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 6 — 18 November 2011

© NXP B.V. 2011. All rights reserved.

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