STL18N60M2(2014) Просмотр технического описания (PDF) - STMicroelectronics

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STL18N60M2
(Rev.:2014)

N-channel 600 V, 0.278 Ω typ., 9 A MDmesh II Plus™ low Qg Power MOSFET in a PowerFLAT™ 5x6 HV package

STMicroelectronics 

Electrical characteristics

2

Electrical characteristics

STL18N60M2

(TC = 25 °C unless otherwise specified)

Symbol

Parameter

Table 4. On /off states

Test conditions

Drain-source

V(BR)DSS breakdown voltage

VGS = 0, ID = 1 mA

Zero gate voltage

IDSS

drain current

IGSS

Gate-body leakage

current

VGS = 0, VDS = 600 V

VGS = 0, VDS = 600 V,

TC= 125 °C

VDS = 0, VGS = ± 25 V

VGS(th)

RDS(on)

Gate threshold voltage VDS = VGS, ID = 250 μA

Static drain-source

on-resistance

VGS = 10 V, ID = 4.5 A

Min. Typ. Max. Unit

600

V

1 μA

100 μA

100 nA

2

3

4V

0.278 0.308 Ω

Symbol

Parameter

Table 5. Dynamic

Test conditions

Min. Typ. Max. Unit

Ciss

Coss

Crss

Input capacitance

Output capacitance

Reverse transfer

capacitance

VGS = 0, VDS = 100 V,

f = 1 MHz,

-

791

- pF

-

40

- pF

-

1.3

- pF

(1) Output equivalent

Coss eq. capacitance

VGS = 0, VDS = 0 to 480 V

- 164.5 - pF

Intrinsic gate

RG resistance

f = 1 MHz, ID=0

-

5.6

-

Ω

Qg Total gate charge

VDD = 480 V, ID = 13 A,

Qgs Gate-source charge VGS = 10 V

Qgd Gate-drain charge

(see Figure 15)

- 21.5 - nC

-

3.2

- nC

- 11.3 - nC

1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS

increases from 0 to 80% VDS.

4/16

DocID026517 Rev 1

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