M48T128V(2010) Просмотр технического описания (PDF) - STMicroelectronics
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M48T128V Datasheet PDF : 23 Pages
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M48T128Y, M48T128V
2
Operation modes
Operation modes
Note:
Figure 3 on page 6 illustrates the static memory array and the quartz controlled clock
oscillator. The clock locations contain the year, month, date, day, hour, minute, and second
in 24 hour BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day
months are made automatically. Byte 1FFF8h is the clock control register. This byte controls
user access to the clock information and also stores the clock calibration setting. The seven
clock bytes (1FFFFh - 1FFF8h) are not the actual clock counters, they are memory locations
consisting of BiPORT™ READ/WRITE memory cells within the static RAM array. The
M48T128Y/V includes a clock control circuit which updates the clock bytes with current
information once per second. The information can be accessed by the user in the same
manner as any other location in the static memory array. The M48T128Y/V also has its own
power-fail detect circuit. This control circuitry constantly monitors the supply voltage for an
out of tolerance condition. When VCC is out of tolerance, the circuit write protects the
TIMEKEEPER® register data and external SRAM, providing data security in the midst of
unpredictable system operation. As VCC falls below the battery backup switchover voltage
(VSO), the control circuitry automatically switches to the battery, maintaining data and clock
operation until valid power is restored.
Table 2. Operating modes
Mode
VCC
E
G
W DQ0-DQ7
Deselect
WRITE
READ
4.5 to 5.5 V
or
3.0 to 3.6 V
VIH
X
X
VIL
X
VIL
VIL
VIL
VIH
READ
VIL
VIH
VIH
Deselect VSO to VPFD (min)(1) X
X
X
Deselect
≤ VSO(1)
X
X
X
High Z
DIN
DOUT
High Z
High Z
High Z
1. See Table 11 on page 18 for details.
X = VIH or VIL; VSO = battery backup switchover voltage.
Power
Standby
Active
Active
Active
CMOS standby
Battery backup mode
Doc ID 5746 Rev 6
7/23
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