PI6C2516A Просмотр технического описания (PDF) - Pericom Semiconductor Corporation
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PI6C2516A Datasheet PDF : 7 Pages
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PI6C2516
Phase-Locked Loop Clock Driver
with 16 Clock Outputs 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
Timing Requirements (Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature)
Symbol
Parameter
Min.
Max.
Units
FCLKOP
tCLKAPP
tSTABLILIZATION
Operator clock frequency (1)
Application clock frequency(2,4)
Stabilization time after power up(3)
25
150
MHz
6
133
1
ms
DCYI
Input clock duty cycle
40
60
%
Notes:
1. Operating Clock Frequency indicates a range over which the PLL must be able to lock, but in which it is not
required to meet the other timing parameters (used for low-speed system debug).
2. Application Clock Frequency indicates a range over which the PLL must meet all of the timing parameters.
3. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be
obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications
for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable.
4. Frequency and loading condition should not exceed 0.85 watt power dissipation (package limitation). Please refer to Graph 1.
350
300
250
200
150
100
50
0
0
Load = 22pF
Load = 10pF
50
100
150
Clock Frequency (MHz)
Graph 1. Dynamic Current vs. Clock Frequency (VCC = 3.6V, TA = 25°C)
Switching Characteristics
(Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature, CL = 22pF) (1,3)
Parameter
From
(Input)
To
(Output)
VCC = 3.3V ± 0.165V
VCC = 3.3V ± 0.3V
Min. Typ. Max. Min. Typ. Max.
tphase error
tsk(O)(2)
CLKIN↑ = 100MHz
Any Y or FBOUT
FBIN↑
150
+170
200
Jitter(pk-pk)
F(CLKIN > 66MHz)
100
100
Duty cycle
F(CLKIN ≤ 66MHz)
F(CLKIN > 66MHz)
Any Y or FBOUT
45
55
45
55
tr
CLKIN = 50 to 150MHz
tf
from 20% to 80%
1.3 2.1 0.7
2.1
1.7 2.5 1.2
2.5
Notes:
1. These parameters are not production tested.
2. The tsk(O) specification is only valid for equal loading of all outputs.
3. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
Units
ps
%
ns
5
PS8440C 07/24/01
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