GF9101 Просмотр технического описания (PDF) - Unspecified
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GF9101 Datasheet PDF : 23 Pages
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TABLE 1: Configuration Register Format
CONFIGURATION
REGISTER BIT
COEF_DATA(6-0)
MEANING
0
MODE A (1 if A input signed, 0 if unsigned)
1
MODE B (1 if B input signed, 0 if unsigned)
3, 2
DELAY_SEL selects delay for pipelining:
Bits 3, 2
Delay in CLK_IN cycles
0, 0
1
0, 1
3
1, 0
4
1, 1
5
4
DATA_B_SEL 0 selects B12 for two 12 tap
filters or one 24 tap filter by externally
connecting DATA_A_OUT to DATA_B_IN.
DATA_B_SEL 1 selects A12 for a 23 tap
filter.
6,5
LOAD MODE SELECT (see below)
Bits 6, 5
Loading mode
0, 0
Serial
0, 1
Parallel
1, 0
Microprocessor
1, 1
Reserved
TABLE 2: Memory Locations for Internal RAM
MEMORY BANKS (BITS)
TAPS (BITS)
0 (23-12)
0 (11-0)
0 (11-0)
2 (11-0)
1 (23-12)
3 (11-0)
1 (11-0)
4 (11-0)
2 (23-12)
5 (11-0
2 (11-0)
6 (11-0)
3 (23-12)
7 (11-0)
3 (11-0)
8 (11-0)
4 (23-12)
9 (11-0)
4 (11-0)
10 (11-0)
5 (23-12)
11 (11-0)
5 (11-0)
12 (11-0)
PARALLEL LOADING
If parallel loading is selected, both the COEF_WR pin and
the LOAD_EN pin determine whether the GF9101 is in the
load mode. When COEF_WR and LOAD_EN are both low,
the load mode is selected, the run mode is disabled, and
writes to memory can occur. Parallel loading is random
access and synchronous.
Data is written through COEF_DATA (7-0) and its destination
is determined by COEF_ADDR (9-0). Coefficient memory is
loaded by writing 8 bits at a time, first to two temporary
registers (bits 15 -0) and finally to the desired memory bank
(bits 23-0). Each memory bank word is loaded in three
clock cycles. COEF_ADDR (9-7) defines the address
location for temporary registers (TEMP_REG_A and
TEMP_REG_B) and memory banks. COEF_ADDR (6-0)
determines the filter coefficient address (0 -107) in the
internal RAM. COEF_ADDR (6-0) must be less than 108. In
Table 3, COEF_ADDR (9-7) determines the following:
TABLE 3: Temporary Loading Registers and Memory Banks
COEF_ADDR(9-7)
(binary)
DESTINATION
NUMBER OF BITS
111
TEMP_REG_B
8 (15-8)
110
TEMP_REG_A
8 (7-0)
101
MB51
24 (23-0)
100
MB4
24 (23-0)
011
MB3
24 (23-0)
010
MB2
24 (23-0)
001
MB1
24 (23-0)
000
MB0
24 (23-0)
NOTE 1: Memory Bank No. 5
TEMP_REG_A and TEMP_REG_B temporarily hold memory
bits, (7-0) and (15-8) respectively. Three 8 bit writes are
necessary to write one 24-bit memory as follows:
1. Load COEF_DATA (7-0) into TEMP_REG_A
2. Load COEF_DATA (7-0) into TEMP_REG_B
3. Load COEF_DATA (7-0), TEMP_REG_B (7-0), and
TEMP_REG_A (7-0) into the selected memory bank, MB0-
MB5 (23-0).
While COEF_ADDR (9-7) selects MB0-MB5 for writing,
COEF_ADDR (6-0) selects the memory bank location that
the 24-bit word is written into. Parallel loading is
synchronous with CLK_IN. When COEF_WR and LOAD_EN
are both low, 8-bit words will be written on the rising edge of
CLK_IN. Consecutive writes may be done indefinitely by
keeping COEF_WR and LOAD_EN low. A parallel loading
timing diagram is shown in Figure 1.
4
520 - 64 - 7
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