WT8048N3 Просмотр технического описания (PDF) - Weltrend Semiconductor
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WT8048N3 Datasheet PDF : 10 Pages
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eltrend
WT8048
OVERRIDE mode
To initiate Override, both the horizontal and vertical sync signals shall be in the no pulses
condition when the display is manually powered on. This condition should be maintained
during the entire time Override is required. As soon as pulses are detected on either horizontal
or vertical sync signal. The display shall enter DPMS operation.
Three power management pins are open drain structure and active low. If you do not need all
those three power saving states in your design. You can just short two or three pins of the
pins: for example, by shorting pin STD_BY and pin Suspend, you will have only two power
saving stated, that is OFF and Suspend states, so you have three states total, including ON
state.
TYPICAL APPLICATION CIRCUIT
WT8048:
HSIN
1
680
10K
5V
VSIN
2
680
3.3M
10K
10K
3
945
10K
10K
4
12
32768Hz 470P
5V
VCC
8
7
6
5
NOTE:
1. Transistor: 2SC945¡ A£ ]>300¡ C
2. VDD: +5V ± 10%
9
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