WT8048N3 Просмотр технического описания (PDF) - Weltrend Semiconductor
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WT8048N3 Datasheet PDF : 10 Pages
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eltrend
WT8048
The Way WT8048 implements VESA DPMS
As shown on Table 2, when H_SYNC / V_SYNC signals transition from ON state to any one
of the three power saving state, WT8048 will delay 5.9 seconds to meet the VESA DPMS
requirement: the minimum 5 seconds delay to avoid unintentionally entering a power saving
state during display resolution and timing mode changes. If during this delay time period,
H_SYN and V_SYN signals return to ON state, then all three power management pins will
remain ON state. If power management state of H_SYNC and V_SYNC prolong for more
than 5.9 seconds, then these three power management pins will change to the corresponding
states. While changing from any power saving state back to ON state will take about 0.368
second for H_SYNC / V_SYNC pulse checking. And transition between any power saving
state will be done immediately.
Table 2: The truth table of Power Saving Detector
MODE
HSIN
VSIN
STD_B
SUSPEND
OFF
Y
ON
Pulses
Pulses
1
1
1
STAND_BY No Pulses
Pulses
0
1
1
SUSPEND
Pulses
No
0
0
1
Pulses
OFF
No Pulses
No
0
0
0
Pulses
OVERRIDE
No Pulses
No
1
1
1
Pulses
Manually Power On
7
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