MX29L3211MC-10 Просмотр технического описания (PDF) - Macronix International

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MX29L3211MC-10

32M-BIT [4M x 8/2M x 16] CMOS SINGLE VOLTAGE PAGEMODE FLASH EEPROM

Macronix International 

MX29L3211

Table1.PIN DESCRIPTIONS

SYMBOL TYPE

A0 - A20 INPUT

Q0 - Q7 INPUT/OUTPUT

Q8 - Q14 INPUT/OUTPUT

Q15/A -1 INPUT/OUTPUT

CE

INPUT

OE

WE

BYTE

INPUT

INPUT

INPUT

VCC

GND

NAME AND FUNCTION

ADDRESS INPUTS: for memory addresses. Addresses are internally

latched during a write cycle.

LOW-BYTE DATA BUS: Input data and commands during Command Interface

Register(CIR) write cycles. Outputs array,status and identifier data in the

appropriate read mode. Floated when the chip is de-selected or the outputs

are disabled.

HIGH-BYTE DATA BUS: Inputs data during x 16 Data-Write operations.

Outputs array, identifier data in the appropriate read mode; not used for status

register reads. Floated when the chip is de-selected or the outputs are

disabled

Selects between high-byte data INPUT/OUTPUT(BYTE = HIGH) and LSB

ADDRESS(BYTE = LOW)

CHIP ENABLE INPUTS: Activate the device's control logic, Input buffers,

decoders and sense amplifiers. With CE high, the device is deselected and

power consumption reduces to Standby level upon completion of any current

program or erase operations. CE must be low to select the device.

OUTPUT ENABLES: Gates the device's data through the output buffers

during a read cycle OE is active low.

WRITE ENABLE: Controls writes to the Command Interface Register(CIR).

WE is active low.

BYTE ENABLE: BYTE Low places device in x8 mode. All data is then input

or output on Q0-7 and Q8-14 float. AddressQ15/A-1 selects between the high

and low byte. BYTE high places the device in x16 mode, and turns off the Q15/

A-1 input buffer. Address A0, then becomes the lowest order address.

DEVICE POWER SUPPLY(3.3V ± 10%)

GROUND

P/N:PM0641

REV. 0.3, NOV. 06, 2001

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