CXD1948R Просмотр технического описания (PDF) - Sony Semiconductor

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CXD1948R

IEEE1394 Link Layer LSI for DVB and DSS

Sony Semiconductor 

3. Pin Description

Pin

No.

Symbol

I/O

Description

1 Vss

— GND

2 DATA15

I/O I/O data with host I/F BIT 15

3 DATA14

I/O I/O data with host I/F BIT 14

4 DATA13

I/O I/O data with host I/F BIT 13

5 DATA12

I/O I/O data with host I/F BIT 12

6 DATA11

I/O I/O data with host I/F BIT 11

7 DATA10

I/O I/O data with host I/F BIT 10

8 DATA9

I/O I/O data with host I/F BIT 9

9 DATA8

I/O I/O data with host I/F BIT 8

10 VDD

— Power supply

11 DATA7

I/O I/O data with host I/F BIT 7

12 DATA6

I/O I/O data with host I/F BIT 6

13 DATA5

I/O I/O data with host I/F BIT 5

14 DATA4

I/O I/O data with host I/F BIT 4

15 DATA3

I/O I/O data with host I/F BIT 3

16 DATA2

I/O I/O data with host I/F BIT 2

17 DATA1

I/O I/O data with host I/F BIT 1

18 DATA0

I/O I/O data with host I/F BIT 0

19 Vss

20 TEST0

21 TEST1

22 TEST2

23 TEST3

24 TEST4

25 TEST5

26 TEST6

27 TEST7

— GND

— Test pin∗

— Test pin∗

— Test pin∗

— Test pin∗

— Test pin∗

— Test pin∗

— Test pin∗

— Test pin∗

28 Vss

— GND

29 XRESET

I

Master reset signal

0: Active; 1: Non-active

30 X8/16

I

I/O data with host I/F bus select signal

0: 8 bit; 1: 16 bit

31 ADDRESS6 I Host I/F address bus BIT 6

32 ADDRESS5 I Host I/F address bus BIT 5

33 ADDRESS4 I Host I/F address bus BIT 4

34 ADDRESS3 I Host I/F address bus BIT 3

∗ The test pins should be used open.

–5–

CXD1948R

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