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CXD1948R

IEEE1394 Link Layer LSI for DVB and DSS

Sony Semiconductor 

Receive Interface (for sync mode/8 bit/Nbyte)

CXD1948R

AICK

READREQ

PACKETEN

AIREAD

AIDT Don’t Care

0

ERRFLAG

1

2

········ N – 3 N – 2

N–1

Don’t Care

Valid interval for transport stream packet

Sync interface mode is obtained by setting the CFR AsyncAI register to 0. (The default is 0.)

The CXD1948R outputs the first data of the transport stream packet by changing the READREQ output signal

and PACKETEN output signal from low to high when the packet has been completely received and is ready for

output.

The READREQ output signal goes low when the first data is output.

The same as for transmit, the result of subtracting 4 and the value set in the AddSize register from the value

set in the CFR S_PacketSize register is used as the size of the valid data output in one packet. The timing is

done by the AICK rise when AIREAD is high.

The AIREAD signal is used as the enable signal, so the interval that the AIREAD signal is high relative to one

data must be one AICK clock interval. The interval that the AIREAD signal is low relative to one data is not

specified.

The limits on AICK input frequency are given below.

For 8-bit data input: 40MHz (Max.), 2MHz (Min.)

For 16-bit data input: 20MHz (Max.), 2MHz (Min.)

The ERRFLAG input during receive can be made valid by setting the CFR ErrBitEnable register to 1. (The

default is 0.)

The CXD1948R outputs the ERRFLAG at high during the valid interval if the output transport stream packet is

an error.

The switching timing for ERR_FLAG input can be changed in the same way as data switching timing, with

AIREAD signal rise.

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