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CS89712

High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller

Cirrus Logic 

CS89712

2. FUNCTIONAL DESCRIPTION

2.1 CPU Core

The ARM720T consists of an ARM7TDMI 32-bit

RISC processor, a unified 8 kbyte cache, and a

memory management unit (MMU). The cache is

four-way set associative organized as 512 lines

with each line being 16 bytes. The cache is directly

connected to the ARM7TDMI, and therefore cach-

es the virtual address from the CPU. When the

cache misses, the MMU translates the virtual ad-

dress into a physical address. A 64-entry translation

lookaside buffer (TLB) is utilized to speed the ad-

dress translation process and reduce bus traffic nec-

essary to read the page table. The MMU saves

power by only translating cache misses.

See the ARM720T Data sheet for a complete de-

scription of the various logic blocks that make up

the processor, as well as all internal registers.

2.2 State Control

The CS89712 supports the following Power Man-

agement States: Operating, Idle, and Standby (see

Figure 2). There is also a state called the Doze

State, however it is a temporary execution state.

The normal program execution state is the Operat-

ing State, which is a full performance state where

all of the clocks and peripheral logic are enabled.

The Idle State is the same as the Operating State

with the exception of the CPU clock being halted,

and only an external interrupt will return it back to

the Operating State. The Standby State has the low-

est power consumption of the three states. By se-

lecting this mode the main oscillator shuts down,

leaving only the Real-Time Clock and its associat-

ed logic powered. When the CS89712 is in Standby

all power and ground pins should remain connected

to power and ground in order to have a proper sys-

tem wake-up. The only state that Standby can tran-

sition to is the Operating State.

2.2.1 Standby State

The Standby State equates to the system being

switched "off" (i.e., no display, and the main oscil-

lator is shut down). The PLL will be shut down.

In the Standby State, all the system memory and

state is maintained and the system time is kept up-

to-date. The PLL/on-chip oscillator or external os-

cillator is disabled and the system is static, except

for the low-power watch crystal (32 kHz) oscillator

and divider chain to the RTC and LED flasher. The

RUN signal is driven low, therefore this signal can

be used externally in the system to power down

other system modules.

Whenever the CS89712 is in the Standby State, the

external address and data buses are forced low in-

ternally by the RUN signal. This is done to prevent

peripherals that are powered down from draining

Interrupt or rising wakeup

Standby

Write to standby location,

power fail, or user reset

Operating

nPOR, power fail,

or user reset

Interrupt

Write to halt location

Idle

Figure 2. State Diagram

DS502PP2

7

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