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MX28F2100B

2M-BIT [256K x 8/128K x 16] CMOS FLASH MEMORY

Macronix International 

MX28F2100B

When using the Automatic Chip Erase algorithm, note

that the erase automatically terminates when

adequate erase margin has been achieved for the

memory array(no erase verify command is required).

The margin voltages are internally generated in the

same manner as when the standard Erase Verify

command is used.

If the Erase operation was unsuccessful, bit 5 of the

Status Register will be set to a "1", indicating an Erase

Failure. If Vpp was not within acceptable limits after

the Erase command is issued, the state machine will

not execute an erase sequence; in stead, bit 5 of the

Status Register is set to a "1" to indicate an Erase

Failure, and bit 3 is set to a "1" to indentify that Vpp

supply voltage was not within acceptable limits.

The Automatic Set-up Erase command is a command

only operation that stages the device for automatic

electrical erasure of all bytes in the array. Automatic

set-up erase is performed by writing XX30H to the

command register.

To commence Automatic Chip Erase, the command

XX30H must be written again to the command register.

SET-UP AUTOMATIC BLOCK ERASE/ERASE

COMMANDS

The Automatic Block Erase does not require the device

to be entirely pre-programmed prior to executing the

Automatic Set-up Block Erase command and

Automatic Block Erase command. Upon executing the

Automatic Block Erase command, the device

automatically will program and verify the block(s)

memory for an all-zero data pattern. The system is not

required to provide any controls or timing during these

operations.

When the block(s) is automatically verified to contain

an all-zero pattern, a self-timed block erase and verify

begin. The system is not required to provide any

control or timing during these operations.

When using the Automatic Block Erase algorithm, note

that the erase automatically terminates when adequate

erase margin has been achieved for the memory array

(no erase verify command is required). The margin

voltages are internally generated in the same manner

as when the standard Erase Verify command is used.

The Automatic Set-up Block Erase command is a com-

mand only operation that stages the device for auto-

matic electrical erasure of selected blocks in the array.

Automatic Set-up Block Erase is performed by writing

XX20H to the command register. To enter Automatic

Block Erase, the user must write the command D0H to

the command register. Block addresses selected are

loaded into internal register on the second falling edge

of WE. Each successive block load cycle started by the

falling edge of WE must begin within 30us from the

rising edge of the preceding WE. Otherwise, the

loading period ends and internal auto block erase cycle

starts.

ERASE SUSPEND

This command only has meaning while the state ma-

chine is executing Automatic Chip/Block Erase opera-

tion, and therefore will only be responded to during

Automatic Chip/Block Erase operation. It is noted that

Erase Suspend is meaningful for block erase only after

block addresses load are finished (100 us after the last

address is loaded). After this command has been ex-

ecuted, the command register will initiate erase sus-

pend mode. The state machine will set DQ7, DQ6 as 1,

1, after suspend is ready. At this time, state machine

only allows the command register to respond to the

Read Memory Array, Erase Resume and Read Status

Register.

P/N: PM0382

REV. 1.5, MAR. 24, 1998

8

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