MX28F2100B Просмотр технического описания (PDF) - Macronix International
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MX28F2100B Datasheet PDF : 45 Pages
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MX28F2100B
DATA PROTECTION
The MX28F2100B is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transition.
During power up the device automatically resets the state
machine in the Read mode. In addition, with its control
register architecture, alteration of the memory contents
only occurs after successful completion of specific
command sequences. The device also incorporates
several features to prevent inadvertent write cycles
resulting from VCC power-up and power-down transition
or system noise.
LOW VPP WRITE INHIBIT
To avoid initiation of a write cycle during VPP power-up
and power-down a write cycle is locked out for VPP less
than VPPLK(typically 9V). If VPP < VPPLK, the command
register is disabled and all internal program/erase circuits
are disabled. Subsequent writes will be ignored until the
VPP level is greater than VPPLK. It is the user's responsibility
to ensure that the control pins are logically correct to
prevent unintentional write when VPP is above VPPLK.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns(typical) on CE or WE will not
initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL, CE =
VIH or WE = VIH. To initiate a write cycle CE and WE must
be a logical zero while OE is a logical one.
POWER SUPPLY DECOUPLING
In order to reduced power switching effect, each device
should have a 0.1uF ceramic capacitor connected between
its VCC and GND, and between its VPP and GND.
VPP TRACE ON PRINTED CIRCUIT BOARD
Programming flash memories, while they reside in the
target system, requires that the printed circuit board
designer pay attention to the Vpp power supply trace.
The Vpp pin supplies the memory cell current for
programming. Use similar trace widths and layout
considerations given to the Vcc power bus. Adequate
Vpp supply traces and decoupling will decrease Vpp
voltage spikes and overshoots.
DEEP POWER DOWN MODE
This mode is enabled by RP pin. During Read modes, RP
going low deselects the memory and place the output
drivers in a high-Z state.
In erase or program modes, RP low will abort erase or
program operations, but the memory contents are no
longer valid as the data has been corrupted by RP
function. RP transition to VIL, or turning power off to the
device will clear up Status Register and automatically
defaults to the read array mode.
POWER-UP SEQUENCE
The MX28F2100B powers up in the Read only mode. In
addition, the memory contents may only be altered after
successful completion of a two-step command sequence.
Vpp and Vcc power up sequence is not required.
P/N: PM0382
REV. 1.5, MAR. 24, 1998
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