CS5124XD8 Просмотр технического описания (PDF) - Cherry semiconductor
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CS5124XD8 Datasheet PDF : 10 Pages
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Block Diagram
VCC
UVLO
BIAS
(CS5124 ONLY)
SS
{CS5126 ONLY}
SYNC
VCC UVLO COMP
VCC
+
V 7.7 V/7.275V
LINE UVLO COMP
-
+
TSHUT
150°C/125°C
+
V
2.62 V/2.45V
REMOTE
(SLEEP) COMP
+
V 1.91 V/1.83V
G2
VREF = 5V
ENABLE
OSC
DIS
RAMP
RQ
G1
F1
S
-
V+REFOK
V5REF
RESET DOMAIN
{85 mV/us}
170mV us
+
V
V5REF
G3
-
10µA
VFB COMP
+
+
V 490mV {1/5}
1/10
PWM COMP -
÷
+ +V
{125mV}
60mV
1000Ω
VCC
2.9 R
LINE AMP -
+
+
R
2.0V V
SOFT START LATCH
F2
G5 S Q
R
SET DOMAIN
-
+
SS COMP
+
275mV V
{525mV}
275mV
2ND ICOMP
+
V
{2.65V}
2.90V
+
V
BLANK
G6
V5REF
1.32V
+V
BLANKING
F3
SQ
R
DRIVER
V5REF
G7
4500Ω
SS AMP
GATE
VFB
ISENSE
Gnd
Theory of Operation
Powering the IC
VCC can be powered directly from a regulated supply
and requires 500µA of start-up current. The CS5124/6
includes a line bias pin (BIAS) that can be used to control a
10µA. As the capacitor charges, a buffered version of the
capacitor voltage appears on the VFB pin and the VFB volt-
age begins to rise. As VFB rises the duty cycle increases
until the supply comes into regulation.
series pass transistor for operation over a wide input volt-
age. The BIAS pin will control the gate voltage of an N-
channel MOSFET placed between VIN and VCC to regulate
VCC at 8V.
Soft Start
Soft Start is accomplished by clamping the VFB pin 1.32V
below the SS pin during normal start up and during restart
after a fault condition. When the CS5124/6 starts, the Soft
VCC and UVLO Pins
The UVLO pin has three different modes; low power shut-
down, Line UVLO, and normal operation. To illustrate
how the UVLO pin works; assume that VIN, as shown in
the application schematic, is ramped up starting at 0V with
the UVLO pin open. The SS and ISENSE pins also start at 0V.
While the UVLO is below 1.8V, the IC will remain in a low
Start capacitor is charged from a 10µA source from 0V to
4.9V. The VFB pin follows the Soft Start pin offset by –1.32V
until the supply comes into regulation or until the Soft
Start error amp is clamped at 2.9V (2.65V for the CS5126).
During fault conditions the Soft Start capacitor is dis-
charged at 10mA.
current sleep mode and the BIAS pin of the CS5124 is inter-
nally clamped to a maximum of 15V. When the voltage on
the UVLO pin rises to between 1.8V and 2.6V the reference
for the VCC UVLO is enabled and VCC is regulated to 8V by
the BIAS pin (CS5124 only), but the IC remains in a UVLO
state and the output driver does not switch. When the
UVLO pin exceeds 2.6V and the VCC pin exceeds 7.7V, the
GATE pin is released from a low state and can begin
switching based on the comparison of the ISENSE and VFB
pins. The Soft Start capacitor begins charging from 0V at
Fault Conditions
The CS5124/6 recognizes the following faults: UVLO off,
Thermal Shutdown, VREF(OK), and Second Current
Threshold. Once a fault is recognized, fault latch F2 is set
and the IC immediately shuts down the output driver and
discharges the Soft Start capacitor. Soft Start will begin
only after all faults have been removed and the Soft Start
capacitor has been discharged to less than 0.275V. Each
fault will be explained in the following sections.
5
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