PHD101NQ03LT Просмотр технического описания (PDF) - NXP Semiconductors.

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PHD101NQ03LT

N-channel TrenchMOS logic level FET

NXP Semiconductors. 

NXP Semiconductors

PHD101NQ03LT

N-channel TrenchMOS logic level FET

2. Pinning information

Table 2. Pinning information

Pin

Symbol Description

1

G

gate

2

D

drain

3

S

source

mb

D

mounting base; connected to

drain

[1] It is not possible to make a connection to pin 2.

Simplified outline

mb

[1]

2

1

3

SOT428

(SC-63; DPAK)

3. Ordering information

Graphic symbol

D

G

mbb076 S

Table 3. Ordering information

Type number

Package

Name

PHD101NQ03LT SC-63; DPAK

Description

plastic single-ended surface-mounted package (DPAK); 3 leads

(one lead cropped)

Version

SOT428

PHD101NQ03LT_4

Product data sheet

Rev. 04 — 9 June 2009

© NXP B.V. 2009. All rights reserved.

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