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PHD101NQ03LT

N-channel TrenchMOS logic level FET

NXP Semiconductors. 

PHD101NQ03LT

N-channel TrenchMOS logic level FET

Rev. 04 — 9 June 2009

Product data sheet

1. Product profile

1.1 General description

Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic

package using TrenchMOS technology. This product is designed and qualified for use in

computing, communications, consumer and industrial applications only.

1.2 Features and benefits

„ Low conduction losses due to low

on-state resistance

„ Simple gate drive required due to low

gate charge

„ Suitable for logic level gate drive

sources

1.3 Applications

„ DC-to-DC convertors

1.4 Quick reference data

Table 1. Quick reference

Symbol Parameter

Conditions

VDS

drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C

ID

drain current

Tmb = 25 °C; VGS = 10 V;

see Figure 1; see Figure 3

Ptot

total power

dissipation

Tmb = 25 °C; see Figure 2

Dynamic characteristics

QGD

gate-drain charge VGS = 5 V; ID = 50 A;

VDS = 15 V; Tj = 25 °C;

see Figure 11

Static characteristics

RDSon

drain-source

on-state resistance

VGS = 10 V; ID = 25 A;

Tj = 25 °C; see Figure 9;

see Figure 10

Min Typ Max Unit

-

-

30 V

-

-

75 A

-

-

166 W

-

8

-

nC

-

4.5 5.5 mΩ

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