MB90440G Просмотр технического описания (PDF) - Fujitsu
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MB90440G Datasheet PDF : 61 Pages
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MB90440G Series
s FEATURES
• Clock
Internal PLL clock multiplication circuit
Base oscillation divided into two or multiplied by one to four
Minimum execution time : 62.5 ns (4 MHz oscillation, PLL clock multiplication multiplier = 4, VCC = 5.0 V)
32 kHz subsystem clock
• Instruction set optimized for controller applications
Supported data types : bit, byte, word, and long-word types
Standard addressing modes : 23 types
Singed multiplication/division and extended RET1 instructions
32-bit accumulator enhancing high-precision operations
• Enhanced high level language (C) and multi-tasking support instructions
Use of a system stack pointer
Symmetrical instruction set and barrel shift instructions
• Program patch function (for two address pointers)
• Enhanced execution speed : 4 byte instruction queue
• Enhanced interrupt function : 8 priority levels programmable and 34 causes
• Automatic data transmission function independent of CPU operation
Extended intelligent I/O service function (EI2OS)
• Internal ROM size and type
FLASH ROM : 128 Kbytes
Internal RAM size : 6 Kbyte and 14 Kbyte (evaluation chip)
• FLASH ROM
Supports automatic programming function, Embedded Algorithm*
Writing command/erase command/erase suspend and resume command
Algorithms completion flag
Hardwire reset vector to show the fixed boot code sector
Can be erased by each sector
Sector protection by external programming voltage
• Low-power consumption (stand-by) modes
Sleep mode (CPU operating clock stops)
Stop mode (Main oscillation stops)
CPU intermittent operation mode
Watch mode
Time-base timer mode
• General-purpose I/O ports : 81 ports
• Timers
Watchdog timer : 1 channel
8/16-bit PPG timer : 8/16-bit × 4 channels
16-bit reload timer : 2 channels
* : Embedded Algorithm is a trademark of Advanced Micro Devices, Inc.
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