KL5KUSB201 Просмотр технического описания (PDF) - Unspecified

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KL5KUSB201

USB2.0 Compliant Transceiver Chip Datasheet (Digest)

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Kawasaki USB device

KL5KUSB201

Datasheet (digest) rev 1.1E page 4/21

Table of Contents

1. Overview

5

1.1 Chip Functionality

5

1.2 KL5KUSB201 Product Feature

6

2. Chip Architecture

6

3. Application Example

8

4. Pinout Diagram

8

5. Package Information

9

5.1 Top View

9

5.2 Package Size

10

5.3 Pin Assignment

10

6. Signal Description

11

7. SIE Bus Timing

13

7.1 SIE Bus Output Timing

13

7.2 SIE Bus Input Timing

13

8. USB Bus Timing

14

8.1 Bulk IN Transaction

14

8.2 Bulk OUT Transaction

15

9. USB2.0 LSI Family

15

9.1 T&MT Evaluation Daughter Card (UUT)

15

9.2 PCI Evaluation Add-in Card

16

9.3 KL5BUDV002 LSI (U2PCI)

17

9.4. USB201 and HS_SIE ASIC IP

19

9.4.1 HS_SIE ASIC IP

19

9.4.2 USB201 ASIC IP

20

10. References

21

Copyright © 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.

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