IR5001 Просмотр технического описания (PDF) - International Rectifier
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IR5001 Datasheet PDF : 13 Pages
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IR5001
DETAILED PIN DESCRIPTION
Vline and Vcc
Vline and Vcc are the input and output pins of
the internal shunt regulator. The internal shunt
regulator regulates the Vcc voltage at ~12V. The
Vcc pin should always be by-passed with a ceramic
capacitor to the Gnd pin.
Both Vline and Vcc pins can be used for biasing
the IR5001, as shown in Fig. 16. The Vline pin is
designed to bias the IR5001 directly when the
available bias voltage is above 25V and less than
100V (targeted at typical 36V – 75V telecom
applications). This connection is shown in Fig 16.a.
If the available Vbias voltage is lower than 25V, then
the IC must be biased using Vcc pin and an external
bias resistor as shown in Fig. 16.b. If the available
bias voltage is above 100V, both Vline and Vcc pins
can be used with an external bias resistor. For
calculation of the proper bias resistor value, see
example below.
IR5001
Vline
OUT
Vcc
Gnd
+
Vbias
FETch
INN
FETst
INP
Rbias
+
Vbias
a)
IR5001
Vline
OUT
Vcc
Gnd
FETch
INN
FETst
INP
b)
Figue 16 - Biasing options for IR5001
An example of Rbias calculation is given below.
Vbias voltages used in the example are referenced
to IR5001 Gnd:
Vbias min = 12V
Vbias max = 16V
Rbias = (Vbias min – Vcc UVLOmax) / Icc min =
= (12V – 10.9V) / 0.5mA = 2.2kOhm
Next, using a minimum Vcc (10.2V), verify that Icc
with the selected Rbias will be less than 5mA:
Icc max = (Vbias max – Vcc min)/Rbias =
= (16V - 10.2V) / 2.2kOhm = 2.6mA
Since 2.6mA is below 5mA max Icc, the calculated
Rbias (2.2kOhm) can be used in this design.
INP and INN Inputs
INP and INN are the inputs of the internal high-
speed comparator. Both pins have integrated on-
board voltage clamps and high-voltage 70kOhm
resistors.
In a typical application, INP should be connected
to the source of the N-FET and INN to the drain. To
improve the noise immunity, the connections from
INN and INP pins to the source and drain terminals
of the N-FET should be as short as possible.
The (INP – INN) voltage difference determines
the state of the Vout pin of the IR5001. When the
body diode of the Active ORing N-FET is forward-
biased and the current first starts flowing, the
voltage difference INP – INN will quickly rise toward
~700mV (typical body diode forward voltage drop).
As soon as this voltage exceeds Vhyst – Vos
(27mV typical), the Vout of the IR5001 will be pulled
high, turning the channel of the active ORing FET
on. As the channel of the N-FET becomes fully
enhanced, the (INP – INN) will reduce and stabilize
at the value determined by the source-drain current,
Isd, and Rds(on) of the N-FET:
(INP – INN) steady state = Isd * RDS(on).
When the Vcc pin is used for biasing the
IR5001, the Vbias must always be higher than the
maximum value of the Vcc UVLO threshold (10.9V).
The Rbias resistor should always be connected
between the Vbias voltage source and Vcc pin. The
Rbias resistor is selected to provide adequate Icc
current for the IC. The minimum required Icc to
guarantee proper IC operation under all conditions is
0.5mA. The maximum Icc is specified at 5mA.
If for some reason (due to a short-circuit failure of
the source, for example), the current reverses
direction and tries to flow from drain to source, the
(INP – INN) will become negative; The IR5001 will
then quickly pull its output low, switching the ORing
FET off. For considerations regarding the selection
of the Active ORing N-FET and RDS(on), see
Applications Information Section.
The offset voltage of the internal high-speed
comparator is centered around negative 4mV, and is
always less than 0mV. This asymmetrical offset
8
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