HMS81004E/08E/16E/24E/32E
6. PORT STRUCTURES
R0[0:7]
LVD
Circuit
OTP : connected
MASK : option (default connected)
VDD
Pull up
Reg.
Pull-up Tr.
Open Drain
Reg.
VDD
Data Reg.
Dir. Reg.
VSS
MUX
Rd
Key Scan
Input
KS_EN
MUX
Standby Release Level Control Register
Pin
Tr.: Transistor
Reg.: Register
R10, R13
LVD
Circuit
OTP : connected
MASK : option (default connected)
VDD
Pull up
Reg.
Pull-up Tr.
Open Drain
Reg.
VDD
Data Reg.
Function Sele-
Pin
ction Reg.
VSS
Dir Reg.
Key Scan
Input
MUX
Rd
MUX
KS_EN
Standby Release Level Control Register
Tr.: Transistor
Reg.: Register
R11/INT1, R12/INT2, R14/EC
LVD
Circuit
OTP : connected
MASK : option (default connected)
VDD
Pull up
Reg.
Pull-up Tr.
Open Drain
Reg.
VDD
Data Reg.
Function Sele-
Pin
ction Reg.
VSS
Dir Reg.
to R11...INT1
to R12...INT2
to R14...EC
MUX
Rd
Noise
Filter
Key Scan
Input
MUX
KS_EN
Standby Release Level Control Register
Tr.: Transistor
Reg.: Register
10
JUNE 2001 Ver 1.00