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ML4813CP

Flyback Power Factor Controller

Micro Linear Corporation 

ML4813

FUNCTIONAL DESCRIPTION

OSCILLATOR

The ML4813 oscillator charges the external capacitor (CT)

with a current (ISET) equal to 5/RSET. When the capacitor

voltage reaches the upper threshold, the comparator

changes state and the capacitor discharges to the lower

threshold through Q1. While the capacitor is discharging,

Q2 provides a high pulse.

The oscillator period can be described by:

t OSC = t RAMP + t DEADTIME

(1)

where:

t RAMP

=

CT

ISET

(2)

and:

t DEADTIME

=

CT

8.4mA - ISET

(3)

A graph showing the relationship between RT, CT, the

oscillator frequency, and maximum duty cycle is given in

Figure 1. A pulse of a duration shorter than tDEADTIME

from an external frequency source set to a higher

frequency than fOSC can be applied to pin SYNC to

synchronize the oscillator. RSYNC and CSYNC shorten

longer pulses, as shown in Figure 2.

OUTPUT DRIVER STAGE

The ML4813 output driver is a 1A peak output high speed

totem-pole circuit designed to quickly drive capacitive

loads such as MOSFET gates. See Figure 3 for the output

saturation characteristics for sourcing and sinking current.

ERROR AMPLIFIER

The ML4813 error amplifier is a high open loop gain,

wide bandwidth amplifier. See Figure 4 for the gain and

phase plot.

UN-COMMITTED OP-AMP

The ML4813 contains an uncommitted op amp which is

normally configured as a differencing amplifier to sense

the output voltage. The output voltage in the flyback

configuration is not ground referenced. The op amp in the

ML4813 is a PNP input amplifier similar to the LM324

but with an open emitter class A output stage.

REFERENCE

The reference output voltage versus output current

characteristic is shown in Figure 5.

UNDERVOLTAGE LOCKOUT

On power-up, the ML4813 is in the UVLO condition;

6

10

8

10nF

5nF 2nF

5

90%

1nF

3

20nF

2

85%

80%

70%

1

10

100

1000

OSCILLATOR FREQUENCY (kHz)

Figure 1. Oscillator Timing Resistance vs. Frequency

EXTERNAL

CLOCK

CSYNC

RSYNC

SYNC

10

ISET

RT

9

RT

ISET

CT

16

+

CT

8.4mA

5.6V -

CLOCK

TD

RAMP PEAK

V(CT)

RAMP VALLEY

Figure 2. Oscillator Block Diagram

output low and quiescent current low. The ML4813

becomes operational when VCC reaches 16V. When VCC

drops below 10V, the UVLO condition is re-imposed.

During UVLO, the VREF pin is off, making it usable as a

"flag" for starting up a down-stream PWM converter.

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