CY62146EV30 Просмотр технического описания (PDF) - Cypress Semiconductor

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CY62146EV30

4-Mbit (256 K × 16) Static RAM

Cypress Semiconductor 

CY62146EV30 MoBL®

Switching Waveforms

Figure 5. Read Cycle 1 (Address Transition Controlled) [19, 20]

tRC

ADDRESS

DATA I/O

tOHA

tAA

PREVIOUS DATA VALID

DATAOUT VALID

Figure 6. Read Cycle No. 2 (OE Controlled) [20, 21]

ADDRESS

CE

OE

BHE/BLE

DATA I/O

VCC

SUPPLY

CURRENT

tRC

tACE

tDOE

tLZOE

tDBE

tLZBE

HIGHIMPEDANCE

tLZCE

tPU

50%

tPD

tHZCE

tHZOE

DATAOUT VALID

tHZBE

HIGH

IMPEDANCE

ICC

50%

ISB

Notes

19. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.

20. WE is HIGH for read cycle.

21. Address valid before or similar to CE and BHE, BLE transition LOW.

Document Number: 38-05567 Rev. *H

Page 8 of 18

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