CS8129
ELECTRICAL CHARACTERISTICS (−40°C ≤ TA ≤ 125°C, −40 ≤ TJ ≤ 150°C, 6.0 ≤ VIN ≤ 26 V, 5.0 mA ≤ IOUT ≤ 500 mA,
RRESET = 4.7 kW to VOUT unless otherwise noted.) (Note 3)
Characteristic
Test Conditions
Min
Typ
Max
Unit
OUTPUT STAGE (VOUT)
Output Voltage
−
4.85
5.0
5.15
V
Dropout Voltage
Supply Current
Line Regulation
Load Regulation
Ripple Rejection
Current Limit
IOUT = 500 mA
IOUT = 10 mA
IOUT = 100 mA
IOUT = 500 mA
6.0 V ≤ VIN ≤ 26 V, IOUT = 50 mA
50 mA ≤ IOUT ≤ 500 mA, VIN = 14 V
f = 120 Hz, VIN = 7.0 to 17 V, IOUT = 250 mA
−
−
0.35
0.60
V
−
2.0
7.0
mA
−
6.0
12
mA
−
55
100
mA
−
5.0
50
mV
−
10
50
mV
54
75
−
dB
0.75
1.20
−
A
Overvoltage Shutdown
−
32
−
40
V
Reverse Polarity Input Voltage DC
Thermal Shutdown
VOUT ≥ −0.6 V, 10 W Load
Guaranteed by Design
−15
−30
−
V
150
180
210
°C
RESET AND DELAY FUNCTIONS
Delay Charge Current
RESET Threshold
VDELAY = 2.0 V
VOUT Increasing, VRT(ON)
VOUT Decreasing, VRT(OFF)
5.0
10
15
mA
4.05
4.35
4.50
V
4.00
4.20
4.45
V
RESET Hysteresis
Delay Threshold
VRH = VRT(ON) − VRT(OFF)
Charge, VDC(HI)
Discharge, VDC(LO)
50
150
250
mV
3.25
3.50
3.75
V
2.85
3.10
3.35
V
Delay Hysteresis
−
200
400
800
mV
RESET Output Voltage Low
1.0 V < VOUT < VRT(L), 3.0 kW to VOUT
−
0.1
0.4
V
RESET Output Leakage
VOUT > VRT(H) Current
−
0
10
mA
Delay Capacitor Discharge Voltage
Discharge Latched “ON”, VOUT > VRT
−
0.2
0.5
V
Delay Time
CDELAY = 0.1 mF, (Note 4)
16
32
48
ms
3. To observe safe operating junction temperatures, low duty cycle pulse testing is used in tests where applicable.
4. Assuming ideal capacitor.
Delay Time + CDelay
VDelay Threshold
ICharge
Charge
+
CDelay
3.5
105 (typ)
PACKAGE LEAD DESCRIPTION
PACKAGE LEAD #
SO−16WB
1
16
4, 5, 11, 12, 13
LEAD SYMBOL
VIN
VOUT
GND
Unregulated supply voltage to IC.
Regulated 5.0 V output.
Ground Connection.
FUNCTION
8
Delay
Timing capacitor for RESET function.
6
RESET
CMOS/TTL compatible output lead. RESET goes low whenever VOUT drops below 6.0% of
it’s regulated value.
14
VOUT(SENSE) Remote sensing of output voltage.
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3