74LV259 Просмотр технического описания (PDF) - NXP Semiconductors.

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74LV259

8-bit addressable latch

NXP Semiconductors. 

NXP Semiconductors

74LV259

8-bit addressable latch

VCC

MR input

GND

VOH

Qn output

VOL

VM

tW

tPHL

VM

001aah124

Measurement points are given in Table 9.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 9. The conditional reset input (MR) to output (Qn) propagation delays

VCC

LE input

GND

VCC

D input

GND

VM

tsu

th

VM

tsu

th

VOH

Qn output

Q=D

VM

VOL

Measurement points are given in Table 9.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 10. The data set-up and hold times for the D input to the LE input

Q=D

001aah125

VCC

An input

GND

VCC

LE input

GND

VM ADDRESS STABLE

tsu

th

VM

001aah126

Measurement points are given in Table 9.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 11. The address input set-up and hold times for the An inputs to the LE input

74LV259_3

Product data sheet

Rev. 03 — 2 January 2008

© NXP B.V. 2008. All rights reserved.

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