74LV259 Просмотр технического описания (PDF) - NXP Semiconductors.

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74LV259

8-bit addressable latch

NXP Semiconductors. 

NXP Semiconductors

Table 9. Measurement points

Supply voltage

VCC

< 2.7 V

2.7 V to 3.6 V

Input

VM

0.5VCC

1.5 V

74LV259

8-bit addressable latch

Output

VM

0.5VCC

1.5 V

VCC

VI

PULSE

GENERATOR

VO

D.U.T.

RT

CL

50 pF

RL

1 kΩ

001aaa663

Test data is given in Table 10.

Definitions test circuit:

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

Fig 12. Load circuit for switching times

Table 10. Test data

Supply voltage

VCC

< 2.7 V

2.7 V to 3.6 V

Input

VI

VCC

2.7 V

tr, tf

≤ 2.5 ns

≤ 2.5 ns

74LV259_3

Product data sheet

Rev. 03 — 2 January 2008

© NXP B.V. 2008. All rights reserved.

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