74LV259(2016) Просмотр технического описания (PDF) - NXP Semiconductors.
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74LV259 Datasheet PDF : 19 Pages
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NXP Semiconductors
74LV259
8-bit addressable latch
Table 8. Dynamic characteristics …continued
GND = 0 V; For test circuit see Figure 12.
Symbol Parameter
Conditions
tsu
set-up time
D, An to LE; see Figure 10 and
Figure 11
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
th
hold time
D to LE; see Figure 10
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
th
hold time
An to LE; see Figure 11
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
CPD
power dissipation CL = 50 pF; fi = 1 MHz;
capacitance
VI = GND to VCC
40 C to +85 C
Min Typ[1] Max
-
35
-
24
12
-
18
9
-
[3] 14
7
-
-
30
-
5
10
-
5
8
-
[3]
5
6
-
-
20
-
5
7
-
5
5
-
[3]
5
4
-
[4]
-
19
-
[1] Typical values are measured at Tamb = 25 C.
[2] tpd is the same as tPLH and tPHL.
[3] Typical value measured at VCC = 3.3 V.
[4] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
40 C to +125 C Unit
Min
Max
-
-
ns
29
-
ns
21
-
ns
17
-
ns
-
-
ns
5
-
ns
5
-
ns
5
-
ns
-
-
ns
5
-
ns
5
-
ns
5
-
ns
-
-
pF
74LV259
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 9 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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