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74LV259 Datasheet PDF : 19 Pages
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NXP Semiconductors
74LV259
8-bit addressable latch
10. Dynamic characteristics
Table 8. Dynamic characteristics
GND = 0 V; For test circuit see Figure 12.
Symbol Parameter
Conditions
40 C to +85 C
Min Typ[1] Max
tpd
propagation delay D to Qn; see Figure 8
[2]
VCC = 1.2 V
-
105
-
VCC = 2.0 V
-
36
49
VCC = 2.7 V
-
26
36
VCC = 3.0 V to 3.6 V; CL = 15 pF [3] -
17
-
VCC = 3.0 V to 3.6 V
[3]
-
20
29
tpd
propagation delay An to Qn; see Figure 7
[2]
VCC = 1.2 V
-
105
-
VCC = 2.0 V
-
36
49
VCC = 2.7 V
-
26
36
VCC = 3.0 V to 3.6 V; CL = 15 pF [3] -
17
-
VCC = 3.0 V to 3.6 V
[3]
-
20
29
tpd
propagation delay LE to Qn; Figure 6
[2]
VCC = 1.2 V
-
100
-
VCC = 2.0 V
-
34
48
VCC = 2.7 V
-
VCC = 3.0 V to 3.6 V; CL = 15 pF [3] -
VCC = 3.0 V to 3.6 V
[3]
-
25
35
16
-
19
28
tPHL
HIGH to LOW
MR to Qn; Figure 9
propagation delay VCC = 1.2 V
-
90
-
VCC = 2.0 V
-
31
43
VCC = 2.7 V
-
VCC = 3.0 V to 3.6 V; CL = 15 pF [3] -
VCC = 3.0 V to 3.6 V
[3]
-
23
31
14
-
17
25
tW
pulse width
LE, HIGH or LOW; see Figure 6
VCC = 2.0 V
34
10
-
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
25
8
-
[3] 20
6
-
tW
pulse width
MR, LOW; see Figure 9
VCC = 2.0 V
34
10
-
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
25
8
-
[3] 20
6
-
40 C to +125 C Unit
Min
Max
-
-
ns
-
61 ns
-
45 ns
-
-
ns
-
36 ns
-
-
ns
-
61 ns
-
45 ns
-
-
ns
-
36 ns
-
-
ns
-
60 ns
-
44 ns
-
-
ns
-
35 ns
-
-
ns
-
53 ns
-
39 ns
-
-
ns
-
31 ns
41
-
ns
30
-
ns
24
-
ns
41
-
ns
30
-
ns
24
-
ns
74LV259
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 9 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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