DS1075 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated
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DS1075 Datasheet PDF : 18 Pages
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DS1075
AC ELECTRICAL CHARACTERISTICS
(TA = 0°C to 70°C, VCC = 5V + 5%)
PARAMETER
SYMBOL CONDITION MIN TYP MAX UNITS NOTES
Output Frequency
Tolerance
DfO
VCC = 5V, TA = -0.5 0 +0.5
%
25°C
Combined Freq.
Variation
DfO
Over temp and -1
voltage
+1
%
Long Term Stability
DfO
-0.5
+0.5 %
Maximum Input
Frequency
fOSCIN
External clock
Crystal reference
50 MHz
25 MHz
1
Minimum Output
fOUT
Frequency
29.3
kHz
2
Power-Up Time
tpor + tstab
0.1 1
ms
3, 4
Enable OUT from PDN ↑
tstab
0.1 1
ms
4
Enable OUT0 from
tstab
0.1 1
ms
4, 5
PDN ↑
OUT Hi-Z from PDN ↓
tpdn
1
ms
OUT0 Hi-Z from PDN ↓
tpdn
1
ms
Load Capacitance
CL
(IN/OUT, OUT0)
15
pF
6
Output Duty Cycle
40
60
%
IN/OUT, OUT0
40
60
%
Jitter
J
100 pS
7
NOTES:
1. This is the maximum frequency which can be applied to OSCIN, or, the maximum crystal frequency
that can be used.
2. The values of M, N and the frequency of OSCIN (if used) must be chosen so that this spec is met.
3. This is the time from when VCC is applied until the output starts oscillating.
4. When the device is initially powered up, or restored from the power-down mode, OE should be
asserted (high). Otherwise the start of the tstab interval will be delayed until OE goes high. OE can
subsequently be returned to a low level during the tstab interval to force out low after the tstab interval.
If the external mode is selected tstab will be a function of the OSCIN period, i.e., external clock
frequency. See “Calculated Parameters” to determine the value of tstab in this case.
5. Although OE does not normally affect OUT0 operation, if OE is held low during power-up the start of
the tstab period will be delayed until OE is asserted. If OE remains low, OUT0 will not start.
6. Operation with higher capacitive loads is possible but may impair output voltage swing and maximum
operation frequency.
7. Parameter given is a typical max.
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