MAX532 Просмотр технического описания (PDF) - Maxim Integrated
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MAX532 Datasheet PDF : 16 Pages
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Dual, Serial-Input,
Voltage-Output, 12-Bit MDAC
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 11.4V to 16.5V, VSS = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VREFA and VREFB = +10V, RL = 2kΩ, CL = 100pF,
VOUT_ connected to RFB_, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
DIGITAL INPUTS (SCLK, DIN, LDAC, CS)
Input High Voltage
VINH
Input Low Voltage
VINL
Input Current
Digital inputs at 0V or VDD
Input Capacitance (Note 2)
MIN TYP MAX UNITS
2.4
V
0.8
V
±1
µA
8
pF
DIGITAL OUTPUT (DOUT) (Note 3)
Output Voltage Low
Output High Leakage
VOL
ILKG
ISINK = 5mA
ISINK = 16mA
VDOUT = 0V to VDD
0.08 0.4
V
0.2
±10
µA
Output High Capacitance
(Note 2)
COUT
15
pF
ANALOG OUTPUTS (VOUTA, VOUTB)
DC Output Impedance
Short-Circuit Current
VOUTA, VOUTB connected to AGNDA, AGNDB
Output Voltage Swing
POWER REQUIREMENTS
Positive Supply Voltage
VDD
Negative Supply Voltage
VSS
0.2
Ω
20
mA
(VDD - 2.5)
to
V
(VSS + 2.5)
11.4
-11.4
16.5
V
-16.5
V
Power-Supply Rejection
∆Full scale/∆VDD, VDD = 11.4V to 16.5V, VREF = -8.9V,
DAC latches loaded with all 1s
PSR
∆Full scale/∆VSS, VSS = -11.4V to -16.5V, VREF = 8.9V,
DAC latches loaded with all 1s
±0.035
±0.035
LSB/%
Positive Supply Current
Negative Supply Current
AC CHARACTERISTICS
IDD Output unloaded
ISS
Output unloaded
5
10
mA
4
6
mA
Voltage-Output
Settling Time
Settling time to within 1/2 LSB of final DAC value; DAC
latch alternately loaded with all 0s and all 1s
2.5
µs
Slew Rate
8
V/µs
Digital-to-Analog
Glitch Impulse
DAC latch alternately loaded with 011...11 and 100...00
60
nV-s
Channel-to-Channel
Isolation
VREFA to VOUTB
VREFA = 20Vp-p 10kHz
sine wave; DAC latches
-100
loaded with all 0s
dB
VREFB = 20Vp-p 10kHz
VREFB to VOUTA
sine wave; DAC latches
-100
loaded with all 0s
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