YMF781 Просмотр технического описания (PDF) - Yamaha Corporation

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YMF781

APL-1 Automobile sound PLayer-1

Yamaha Corporation 

YMF781

TXR

TXF

TXH

TXL

XI

TXFREQ

VIH= 0.75*VDD

VIL= 0.25*VDD

TR

Input Signals

except XI

TF

VIH= 0.75*VDD or 0.75*VDDC

VIL= 0.25*VDD or 025*VDDC

・Clock Sync Serial Interface

Ｉtem

Symbol Ｍin. Ｔyp. Ｍax. Ｕnit

SCLKN frequency (Serial transfer speed)

1 / TSFREQ

1

2

MHz

SCLKN High time

TSH

220

ns

SCLKN Low time

TSL

220

ns

SDI set-up time

TSIS

0

ns

SDI hold time

TSIH

75

ns

SDO output delay time

TSOD

200

ns

SDO output hold time (*1)

TSOH

110

ns

SRDYN output delay time (L→H) (*2)

TSRDD

300

ns

Conditions: TOP= -40 to 85℃, VDD= 3.0 to 3.6V, VDDC= 3.0 to 3.6V or 4.75 to 5.25V, Capacitor load=50pF

(*1) The last SDO output data is held until the next SCLKN falling edge is detected.

(*2) Time to the High level in synchronization with SCLKN, when the first 1 bit is transmitted or received.

The falling timing depends on the transmit/receive process of the internal Control CPU.

SCLKN

SDI

SDO

SRDYN

TSFREQ

TSL

TSH

TSIS

TSIH

TSOD

TSOH

TSRDD

VIH= 0.75*VDDC

VIL= 0.25*VDDC

9

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