XRT91L80 Просмотр технического описания (PDF) - Exar Corporation
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XRT91L80 Datasheet PDF : 45 Pages
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XRT91L80
PRELIMINARY
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
xr
REV. P1.1.0
HARDWARE COMMON CONTROL
NAME
LEVEL
TYPE
PIN
DESCRIPTION
LOOPTM_JA
LVTTL,
I
LVCMOS
C6 Loop Timing Mode With Jitter Attenuation
The LOOPTM_JA pin must be set "High" in order to select the
recovered receive clock as the reference source for the de-jitter
PLL.
"Low" = Disabled
"High" = Loop timing with de-jitter PLL Activated
This pin is provided with an internal pull-down.
LOOPTM_NOJA LVTTL,
I
LVCMOS
P2 Loop Timing Mode With No Jitter Attenuation
When the loop timing mode is activated, the external local refer-
ence clock input to the CMU is replaced with the 1/16th or 1/
32nd of the high-speed recovered receive clock coming from
the CDR.
"Low" = Disabled
"High" = Loop timing Activated
This pin is provided with an internal pull-down.
TRANSMITTER SECTION
NAME
TXDI0P
TXDI0N
TXDI1P
TXDI1N
TXDI2P
TXDI2N
TXDI3P
TXDI3N
LEVEL
LVDS
TXPCLKIP
TXPCLKIN
LVDS
TYPE
I
I
TXOP
TXON
CMLDIFF
O
REFCLKP
LVPECL
I
REFCLKN
VCXO_INP
LVPECL
I
VCXO_INN
PIN
DESCRIPTION
H13 Transmit Parallel Data Input
J13 The 622.08 Mbps 4-bit parallel transmit data input should be
K14 applied to the transmit parallel bus simultaneously to be sam-
L14 pled at the rising edge of the TXPCLKIP/N input. The 4-bit par-
allel interface is multiplexed into the transmit serial output
K13 interface MSB first (TXDI3P/N).
L13
NOTE: The XRT91L80 can accept 666.51 Mbps 4-bit parallel
M14
transmit data input for Forward Error Correction (FEC)
N14
Applications.
H14 Transmit Parallel Clock Input
J14 622.08 MHz clock input used to sample the 4-bit parallel trans-
mit data input TXDI[3:0]P/N.
NOTE: The XRT91L80 can accept a 666.51 MHz transmit clock
input for Forward Error Correction (FEC) Applications.
K1 Transmit Serial Data Output
L1 The transmit serial data output stream is generated by multi-
plexing the 4-bit parallel transmit data input into a 2.488 Gbps
serial data output stream. In Forward Error Correction, the
transmit serial data output stream is 2.666 Gbps.
P6 Reference Clock Input
N6 This differential clock input reference is used for the transmit
clock multiplier unit (CMU) to provide the necessary high-speed
clock reference for this device. Pin ALTFREQSEL determines
the value used as the reference. See Pin ALTFREQSEL for
more details.
P4 Voltage Controled Oscillator Input
N4 This differential clock input is used for the transmit PLL jitter
attenuation. Pin ALTFREQSEL determines the value used as
the reference. See Pin ALTFREQSEL for more details.
6
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