datasheetbank_Logo
Технический паспорт Поисковая и бесплатно техническое описание Скачать

XRT91L80 Просмотр технического описания (PDF) - Exar Corporation

Номер в каталоге
Компоненты Описание
Список матч
XRT91L80 Datasheet PDF : 45 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
XRT91L80
PRELIMINARY
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
xr
REV. P1.1.0
TRANSMITTER SECTION
NAME
LEVEL
TYPE
PIN
DESCRIPTION
TXCLKO16P
TXCLKO16N
LVDS
O
N10 Auxiliary Clock Output (155.52/166.63 MHz)
N11 155.52/166.63 MHz auxiliary clock derived from CMU output.
This clock can also be used for the downstream device as a ref-
erence for generating the TXDI[3:0]P/N data and TXPCLKIP/N
clock input. This enables the downstream device and the STS-
48/STM-16 transceiver to be in synchronization. The output of
this pin is controlled by TXCLKO16DIS.
TXCLKO16DIS
LVTTL,
I
M12 Auxiliary Clock Disable
LVCMOS
This pin is used to control the activity of the auxiliary clock.
"Low" = TXCLKO16P/N Enabled
"High" = TXCLKO16P/N Disabled
This pin is provided with an internal pull-down.
LOCKDET_CMU LVCMOS
O
N2 CMU Lock Detect
This pin is used to monitor the lock condition of the clock multi-
plier unit.
"Low" = CMU Out of Lock
"High" = CMU Locked
OVERFLOW
LVCMOS
O
M13 Transmit FIFO Overflow
This pin is used to monitor the transmit FIFO status.
"Low" = Normal Status
"High" = Overflow Condition
FIFO_RST
LVTTL,
I
LVCMOS
N13 FIFO Control Reset
FIFO_RST should be held "High" for a minimum of 2 TXP-
CLKOP/N cycles after powering up and during manual FIFO
reset. After the FIFO_RST pin is returned "Low," it will take 8 to
10 TXPCLKOP/N cycles for the FIFO to flush out. Upon an
interrupt indication that the FIFO has an overflow condition, this
pin is used to reset or flush out the FIFO.
"Low" = Normal Operation
"High" = Manual FIFO Reset
NOTE: To automatically reset the FIFO, see FIFO_AUTORST
pin.
This pin is provided with an internal pull-down.
FIFO_AUTORST LVTTL,
I
LVCMOS
N12 Automatic FIFO Overflow Reset
If this pin is set "High", the STS-48/STM-16 transceiver will
automatically flush the FIFO upon an overflow condition. Upon
power-up, the FIFO should be manually reset by setting
FIFO_RST "High" for a minimum of 2 TXPCLKOP/N cycles.
"Low" = Manual FIFO reset required for Overflow Conditions
"High" = Automatically resets FIFO upon Overflow Detection
This pin is provided with an internal pull-down.
8

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]