HFA3860B Просмотр технического описания (PDF) - Intersil
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HFA3860B Datasheet PDF : 40 Pages
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HFA3860B
RX_I_IN
RX_Q_IN
A/D_CK
A/D /
3
A/D
/3
+FS OR -FS
COMPARE
+FS OR -FS
COMPARE
TO CORRELATOR
VREFN
ANALOG
BIASES
VREFP
A/D_CAL_POS / 8
A/D_CAL_NEG
/
8
SELECT
8
TO RSSI A/D
ACCUMULATOR
(25-BIT)
D/A
D/A
A/D_CAL_CK
(APPROX 1KHz)
5 MSBs
REG
5
FIGURE 7. A/D CAL CIRCUIT
TEST REG
MODE 1 (7)
A/DCAL
A/D_CAL_ACCUM
(1/4 dB PER LSB)
TEST REG
MODE 25 (8:0)
RSSI A/D Interface
The Receive Signal Strength Indication (RSSI) analog signal is
input to a 6-bit A/D, indicating 64 discrete levels of received
signal strength. This A/D measures a DC voltage, so its input
must be DC coupled. Pin 16 (VREFP) sets the reference for the
RSSI A/D converter. VREFP is common for the I and Q and
RSSI A/Ds. The RSSI signal is used as an input to the Clear
Channel Assessment (CCA) algorithm of the HFA3860B. The
RSSI A/D output is stored in an 6-bit register available via the
TEST Bus and the TEST Bus monitor register. CCA is further
described on page 17.
The interface specifications for the RSSI A/D are listed in
Table 4 below (VREFP = 1.75V).
TABLE 4. RSSI A/D SPECIFICATIONS
PARAMETER
MIN
TYP
MAX
Full Scale Input Voltage
-
-
1.15
Input Bandwidth (0.5dB)
1MHz
-
-
Input Capacitance
-
7pF
-
Input Impedance (DC)
1M
-
-
Test Port
The HFA3860B provides the capability to access a number of
internal signals and/or data through the Test port, pins TEST
7:0. In addition pin 1 (TEST_CK) is an output that can be used
in conjunction with the data coming from the test port outputs.
The test port is programmable through configuration register
(CR28). Any signal on the test port can also be read from
configuration register (CR29) via the serial control port.
There are 32 modes assigned to the PRISM test port. Some
are only applicable to factory test.
TABLE 5. TEST MODES
MODE DESCRIPTION TEST_CLK
TEST (7:0)
0 Quiet Test Bus 0
00
1 RX Acquisition Initial Detect A/DCal, CRS, ED,
Monitor
Track, SFD Detect,
Signal Field Ready,
Length Field Ready,
Header CRC Valid
2 TX Field Monitor IQMARK
A/DCal, TXPE Inter-
nal, Preamble Start,
SFD Start, Signal
Field Start, Length
Field Start, CRC Start,
MPDU Start
3 RSSI Monitor RSSI Pulse CSE Latched, CSE,
RSSI Out (5:0)
4 SQ1 Monitor
Pulse after SQ1 (7:0)
SQ is valid
5 SQ2 Monitor
Pulse after SQ2 (7:0)
SQ is valid
6 Correlator Lo Sample CLK Correlator Magnitude
Rate
(7:0)
7 Freq Test Lo
Rate
Subsample Frequency Register
CLK
(18:11)
8 Phase Test Lo Subsample Phase Register (7:3)
Rate
CLK
Shift <2:0>
9 NCO Test Lo Subsample NCO Register (15:8)
Rate
CLK
10 Bit Sync Accum Enable
(0Ah) Lo Rate
Bit Sync Accum (7:3)
Shift (2:0)
4-10
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