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CS8402A-CS Просмотр технического описания (PDF) - Cirrus Logic

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CS8402A-CS
Cirrus-Logic
Cirrus Logic Cirrus-Logic
CS8402A-CS Datasheet PDF : 34 Pages
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CS8401A
PIN DESCRIPTIONS
CS8401A
DATA BUS BIT 4
D4 1
DATA BUS BIT 5
D5 2
DATA BUS BIT 6
D6 3
DATA BUS BIT 7
D7 4
MASTER CLOCK MCK 5
SERIAL DATA CLOCK
SCK 6
FRAME SYNC FSYNC 7
SERIAL INPUT DATA SDATA 8
ADDRESS BUS BIT 4
A4 9
ADDRESS BUS BIT 3
A3 10
ADDRESS BUS BIT 2
A2 11
ADDRESS BUS BIT 1
A1 12
24 D3
DATA BUS BIT 3
23 D2
DATA BUS BIT 2
22 D1
DATA BUS BIT 1
21 D0
DATA BUS BIT 0
20 TXP
TRANSMIT POSITIVE
19 VD+
POWER
18 GND
GROUND
17 TXN
TRANSMIT NEGATIVE
16 RD/WR READ/WRITE SELECT
15 INT
INTERRUPT
14 CS
CHIP SELECT
13 A0
ADDRESS BUS BIT 0
Power Supply Connections
VD+ - Positive Digital Power, PIN 19.
Positive supply for the digital section. Nominally +5 volts.
GND - Ground, PIN 18.
Ground for the digital section.
Audio Input Interface
SCK - Serial Clock, PIN 6.
Serial clock for SDATA pin which can be configured (via control register 3) as an input or
output, and can sample data on the rising or falling edge. As an output, SCK will contain 32
clocks for every audio sample. As an input, it does not need to be continuous and can be up to
15 MHz.
FSYNC - Frame Sync, PIN 7.
Delineates the serial data and may indicate the particular channel, left or right. Also, FSYNC
may be configured as an input or output. The format is based on bits in control register 3.
SDATA - Serial Data, PIN 8.
Audio data serial input pin.
Parallel Interface
CS - Chip Select, PIN 14.
This input is active low and allows access to the 32 bytes of internal memory. The address bus
and RD/WR must be valid while CS is low.
16
DS60F1

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