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CS8402A-CS

Digital Audio Interface Transmitter

Cirrus Logic 

CS8401A

ples, the user read pointer is reset to 04H (Hex)

and the cycle repeats.

Flag 0 in the status register monitors the position

of the internal user data read pointer. When the

first byte, location 04H, is read, flag 0 is set low

and when the third byte, location 06H, is read,

flag 0 is set high. If mask 0 in control register 1

is set, a transition of flag 0 will generate a low

pulse on the interrupt pin. The value of flag 0

indicates which two bytes the part will read next,

thereby indicating which two bytes are free to be

updated.

Flag 1 is mode dependent, changing with buffer

memory configuration, and is discussed in the

individual buffer mode sections.

Flag 2 is set high when byte 0 of the channel

status, address 08H, is read, and set low when

byte 4, address 0BH, is read. Therefore, flag 2

high indicates the part is reading the first four

bytes of channel status, and the last 20 bytes are

free to update. If the interrupt mask bit for flag 2

is set, the rising edge will cause an interrupt in-

dicating the beginning of a channel status block

as shown in Figure 11. Although a falling edge

Flag 2

Block

(384 Audio Samples)

Flag 1

Mode 0

Flag 1

Modes 1 & 2

Flag 0

23 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 1

Channel Status Byte

(Expanded)

Frame

A0

B0

A1

B1

A2

B2

(Expanded)

A7

B7

bit 0

34

78

Preamble Aux Data LSB

Sub-frame

Audio Data

27 28 29 30 31

MSB V U C P

See figure 15

Validity

User Data

Channel Status Data

Parity Bit

Figure 11. CS8401A Status Register Flag Timing

12

DS60F1

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