PSB4860 Просмотр технического описания (PDF) - Infineon Technologies

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PSB4860

ICs for Communications Sophisticated Answering Machine with Echo Cancellation SAM-EC

Infineon Technologies 

PSB 4860

Figure 44: Memory Management - Structure of Voice Prompt Directory. . . . . . . . . . 80

Figure 45: Audio File Organization - Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 46: Binary File Organization - Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 47: Phrase File Organization - Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 48: Operation Modes - State Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 49: IOM®-2 Interface - Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 50: IOM®-2 Interface - Frame Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 51: IOM®-2 Interface - Single Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 52: IOM®-2 Interface - Double Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 53: IOM®-2 Interface - Channel Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 54: SSDI Interface - Transmitter Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 55: SSDI Interface - Active Pulse Selection . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 56: SSDI Interface - Receiver Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 57: Analog Front End Interface - Frame Structure . . . . . . . . . . . . . . . . . . . . 117

Figure 58: Analog Front End Interface - Frame Start . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 59: Analog Front End Interface - Data Transfer . . . . . . . . . . . . . . . . . . . . . . 118

Figure 60: Status Register Read Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 61: Data Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 62: Register Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 63: Configuration Register Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 64: Configuration Register Write Access or Register Read Command . . . . 122

Figure 65: ARAM/DRAM Interface - Connection Diagram . . . . . . . . . . . . . . . . . . . 127

Figure 66: ARAM/DRAM Interface - Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . 128

Figure 67: ARAM/DRAM Interface - Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . 129

Figure 68: ARAM/DRAM Interface - Refresh Cycle Timing. . . . . . . . . . . . . . . . . . . 129

Figure 69: EPROM Interface - Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 70: EPROM Interface - Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 71: Parallel Flash Memory Interface - Connection Diagram. . . . . . . . . . . . . 131

Figure 72: Parallel Flash Memory Interface - Multiple Devices . . . . . . . . . . . . . . . . 132

Figure 73: Parallel Flash Memory Interface - Command Write . . . . . . . . . . . . . . . . 133

Figure 74: Parallel Flash Memory Interface - Address Write . . . . . . . . . . . . . . . . . . 133

Figure 75: Parallel Flash Memory Interface - Data Write . . . . . . . . . . . . . . . . . . . . 134

Figure 76: Parallel Flash Memory Interface - Data Read . . . . . . . . . . . . . . . . . . . . 134

Figure 77: Serial Flash - Connection to Single TC 58 A 040 F . . . . . . . . . . . . . . . . 135

Figure 78: Serial Flash - Connection to Single AT 45 DB 041 . . . . . . . . . . . . . . . . 135

Figure 79: Serial Flash - Connection to Multiple TC 58 A 040 F . . . . . . . . . . . . . . . 136

Figure 80: Auxiliary Parallel Port - Multiplex Mode . . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 81: Input/Output Waveforms for AC-Tests . . . . . . . . . . . . . . . . . . . . . . . . . . 301

Figure 82: Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

Figure 83: SSDI/IOM®-2 Interface - Bit Synchronization Timing . . . . . . . . . . . . . . . 306

Figure 84: SSDI/IOM®-2 Interface - Frame Synchronization Timing . . . . . . . . . . . . 306

Figure 85: SSDI Interface - Strobe Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

Figure 86: Serial Control Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

Data Sheet

6

2000-01-14

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