PSB4860 Просмотр технического описания (PDF) - Infineon Technologies

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PSB4860

ICs for Communications Sophisticated Answering Machine with Echo Cancellation SAM-EC

Infineon Technologies 

PSB 4860

Table 1

52

53

54

55

62

63

64

65

68

69

70

71

74

75

76

77

42

43

44

45

46

47

50

51

35

36

34

Pin Definitions and Functions

MA0

MA1

MA2

MA3

MA4

MA5

MA6

MA7

MA8

MA9

MA10

MA11

MA12

MA13

MA14

MA15

I/O L2)

I/O L2)

I/O L2)

I/O L2)

I/O L2)

I/O L2)

I/O L2)

I/O L2)

I/O L2)

I/O L2)

I/O L2)

I/O L2)

I/O L2)

I/O L2)

I/O L2)

I/O L2)

Memory Address 0-15:

Multiplexed address outputs for ARAM, DRAM

access.

Non-multiplexed address outputs for voice

prompt EPROM.

Auxiliary Parallel Port:

General purpose I/O.

MD0/

SCLK

I/O -

I/O -

MD1/SDI I/O -

MD2/SDO I/O -

MD3

I/O -

MD4/CS0 I/O -

MD5/CS1 I/O -

MD6/CS2 I/O -

MD7/CS3

CAS0/ALE O

H3)

CAS1/

FCS

O

ARAM/DRAM or Samsung Flash:

Memory data bus.

Serial Flash Memory (Toshiba, Atmel):

Serial interface signals and predecoded chip

select lines.

ARAM, DRAM:

Column address strobe for memory bank 0

or 1.

Flash Memory:

Address Latch Enable for address lines A16-

A23.

Chip select signal for Flash Memory

RAS/FOE O H3) ARAM, DRAM:

Row address strobe for both memory banks.

Flash Memory:

Output enable signal for Flash Memory.

Data Sheet

16

2000-01-14

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