W742E816 Просмотр технического описания (PDF) - Winbond

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W742E816

4-BIT MICROCONTROLLER

Winbond 

W742E/C816

Deleted: SA5505

Deleted: W742C811

5.11 Watchdog Timer (WDT)

The watchdog timer (WDT) is organized as a 4-bit up counter designed to prevent the program from

unknown errors. The WDT can be enabled by mask option code. If the WDT overflows, the chip will be

reset. At initial reset, the input clock of the WDT is FOSC/1024. The input clock of the WDT can be

switched to FOSC/16384 by setting SCR.2 register. The contents of the WDT can be reset by the

instruction CLR WDT. In normal operation, the application program must reset WDT before it

overflows. A WDT overflow indicates that operation is not under control and the chip will be reset. The

WDT overflow period is about 500 mS when the system clock (FOSC) is 32 KHz and WDT clock input

is FOSC/1024. The organization of the Divider0 and watchdog timer is shown in Figure 5-5. The

minimum WDT time interval is 1/(FOSC/16384 x 16) - 1/(FOSC/16384).

Fosc

Divider0

... Q1 Q2

Q9 Q10 Q11 Q12 Q13 Q14

S

EVF.0

Q

R

HEF.0

IEF.0

Hold mode release (HCF.0)

Divider interrupt

Option code is reset to "0"

1. Reset

2. CLR EVF,#01H

3. CLR DIVR0

SCR.2

Fosc/16384

Fosc/1024

Disable

Enable

WDT

Qw1 Qw2 Qw3 Qw4

R

R

R

R

Option code is set to "1"

Overflow signal

System Reset

1. Reset

2. CLR WDT

Figure 5-5. Organization of Divider0 and Watchdog Timer

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