W40S01 Просмотр технического описания (PDF) - Cypress Semiconductor

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W40S01

SDRAM Buffer - 4 DIMM

Cypress Semiconductor 

W40S01-04

Signaling Requirements

As shown in Figure 2, valid data bits are defined as stable logic

0 or 1 condition on the data line during a clock HIGH (logic 1)

pulse. A transitioning data line during a clock HIGH pulse may

be interpreted as a start or stop pulse (it will be interpreted as

a start or stop pulse if the start/stop timing parameters are

met).

A write sequence is initiated by a “start bit” as shown in Figure

3. A “stop bit” signifies that a transmission has ended.

As stated previously, the W40S01-04 sends an “acknowledge”

pulse after receiving eight data bits in each byte as shown in

Figure 4.

Sending Data to the W40S01-04

The device accepts data once it has detected a valid start bit

and address byte sequence. Device functionality is changed

upon the receipt of each data bit (registers are not double buff-

ered). Partial transmission is allowed meaning that a transmis-

sion can be truncated as soon as the desired data bits are

transmitted (remaining registers will be unmodified). Transmis-

sion is truncated with either a stop bit or new start bit (restart

condition).

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Figure 2. Serial Data Bus Valid Data Bit

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Figure 3. Serial Data Bus Start and Stop Bit

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