UPD72870AF1 Просмотр технического описания (PDF) - NEC => Renesas Technology

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UPD72870AF1

IEEE1394 1-CHIP OHCI HOST CONTROLLER

NEC => Renesas Technology 

PIN NAME

µPD72870A

AD0-AD31 : PCI Multiplexed Address and Data

AGND

: Analog GND

CARD_ON : PCI/Card Select

CBE0-CBE3 : Command/Byte Enables

CIS_ON : CIS Register ON

CLKRUN : PCICLK Running

CMC

: Configuration Manager Capable

CPS

: Cable Power Status Input

DEVSEL : Device Select

DGND

: Digital GND

FIL0

: APLL Filter GND

FIL1

: APLL Filter Terminal

FRAME : Cycle Frame

GNT

: Bus_master Grant

GROM_EN : Serial EEPROM Enable

GROM_SCL : Serial EEPROM Clock Output

GROM_SDA : Serial EEPROM Data Input / Output

IC(H)

: Internally Connected (High Clamped)

IC(L)

: Internally Connected (Low Clamped)

IC(N)

: Internally Connected (Open)

IDSEL

: ID Select

INTA

: Interrupt

IRDY

: Initiator Ready

L_VDD

: VDD for Link Digital Core and Link I/Os

PAR

: Parity

PC0-PC2 : Power Class Input

PCI_VDD : VDD for PCI I/Os

PCLK

: PCI Clock

PERR

: Parity Error

PIN_EN : Pin Enable Input

PME

: PME Output

PORTDIS : Port Disable

PRST

: Reset

P_AVDD : PHY Analog VDD

P_DVDD : PHY Digital VDD

P_RESETB : PHY Power on Reset Input

REQ

: Bus_master Request

RI0

: Resistor0 for Reference Current Setting

RI1

: Resistor1 for Reference Current Setting

SERR

: System Error

STOP

: PCI Stop

SUS_RESM : Suspend/Resume Function Select

TpA0n

: Port-1 Twisted Pair A Negative Input/Output

TpA0p

: Port-1 Twisted Pair A Positive Input/Output

TpA1n

: Port-2 Twisted Pair A Negative Input/Output

TpA1p

: Port-2 Twisted Pair A Positive Input/Output

TpA2n

: Port-3 Twisted Pair A Negative Input/Output

TpA2p

: Port-3 Twisted Pair A Positive Input/Output

TpB0n

: Port-1 Twisted Pair B Negative Input/Output

TpB0p

: Port-1 Twisted Pair B Positive Input/Output

TpB1n

: Port-2 Twisted Pair B Negative Input/Output

TpB1p

: Port-2 Twisted Pair B Positive Input/Output

TpB2n

: Port-3 Twisted Pair B Negative Input/Output

TpB2p

: Port-3 Twisted Pair B Positive Input/Output

TpBias0 : Port-1 Twisted Pair Bias Voltage Output

TpBias1 : Port-2 Twisted Pair Bias Voltage Output

TpBias2 : Port-3 Twisted Pair Bias Voltage Output

TRDY

: Target Ready

XI

: X’tal XI

XO

: X’tal XO

Preliminary Data Sheet S14653EJ1V0DS00

9

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